Lines Matching full:due
189 …": "Counts the number of issue slots that were not consumed by the backend due to certain allocati…
197 …ounts the total number of issue slots that were not consumed by the backend due to backend stalls",
203 …unts the total number of issue slots that were not consumed by the backend due to backend stalls. …
207 … slots that were not consumed by the backend because allocation is stalled due to a mispredicted j…
213 … backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue s…
217 … "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which …
222 …due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was …
226 …": "Counts the number of issue slots that were not consumed by the backend due to branch mispredic…
235 … "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which …
243 … "Counts the number of issue slots that were not delivered by the frontend due to the microcode se…
251 …"BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by c…
260 …: "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.",
268 …not consumed by the backend due to a machine clear that does not require the use of microcode, cla…
276 …": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.…
285 … "Counts the number of issue slots that were not delivered by the frontend due to instruction cach…
293 …of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due …
302 … of issue slots that were not delivered by the frontend due to frontend latency restrictions due t…
335 …"BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB m…
340 … of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, …
344 … of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, …
347 "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss",
351 …"PublicDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Lo…
354 …ion": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall…
358 …ion": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall…
361 …"BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB m…
368 … of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, …
372 … of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, …
376 "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss",
380 …"PublicDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Lo…
384 …ion": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall…
388 …ion": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall…
442 "BriefDescription": "Percentage of time that allocation is stalled due to load buffer full",
447 …"BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stati…
452 … "BriefDescription": "Percentage of time that allocation is stalled due to store buffer full",
457 "BriefDescription": "Percentage of time that allocation is stalled due to load buffer full",
463 …"BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stati…
469 … "BriefDescription": "Percentage of time that allocation is stalled due to store buffer full",
523 …"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 mi…
529 …"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 mi…
535 …"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 mi…
541 …"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 mi…
548 …"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 mi…
555 …of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block…
567 … "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full",
573 …he number of machine clears relative to thousands of instructions retired, due to floating point a…
578 …ts the number of machine clears relative to thousands of instructions retired, due to page faults",
583 …he number of machine clears relative to thousands of instructions retired, due to self-modifying c…
610 … "BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss",
615 …"BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeli…
620 "BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk",
625 "BriefDescription": "Percentage of Memory Execution Bound due to a second level TLB miss",
630 … "BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match",
635 … "BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss",
641 …"BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeli…
647 "BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk",
653 "BriefDescription": "Percentage of Memory Execution Bound due to a second level TLB miss",
659 … "BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match",
690 …"BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruc…
695 …"BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruc…
745 … "Counts the number of issue slots that were not delivered by the frontend due to Instruction Tabl…
753 … slots that were not consumed by the backend because allocation is stalled due to a machine clear …
762 …": "Counts the number of issue slots that were not consumed by the backend due to memory reservati…
770 …of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be du…
778 …": "Counts the number of issue slots that were not consumed by the backend due to a machine clear …
786 … "Counts the number of issue slots that were not delivered by the frontend due to other common fro…
794 … "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes…
802 …": "Counts the number of issue slots that were not consumed by the backend due to the physical reg…
810 …": "Counts the number of issue slots that were not consumed by the backend due to the reorder buff…
818 …"BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation",
836 …": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from…