Lines Matching +full:3 +full:- +full:line
4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
31 "Counter": "0,1,2,3",
39 …"BriefDescription": "References per ICache line. This event counts differently than Intel processo…
40 "Counter": "0,1,2,3",
43 …Line. The event strives to count on a cache line basis, so that multiple fetches to a single cach…
48 …"BriefDescription": "References per ICache line that are available in the ICache (hit). This event…
49 "Counter": "0,1,2,3",
52 …Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis…
57 …"BriefDescription": "References per ICache line that are not available in the ICache (miss). This …
58 "Counter": "0,1,2,3",
61 …Line and that cache line is not in the ICache (miss). The event strives to count on a cache line …
67 "Counter": "0,1,2,3",
70 … read from the MSROM. The most common case that this counts is when a micro-coded instruction is …