Lines Matching full:requires
209 …"BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica…
223 …d & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
234 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE…
245 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
256 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
267 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
278 …2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
289 … "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[…
300 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
311 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
322 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
333 …d & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
344 …read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[…
355 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
366 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
377 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
388 …ore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
399 …"PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCO…
410 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
421 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
432 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
443 …d & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
454 …eads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[…
465 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
476 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
487 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
498 …lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
509 …"PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCO…
520 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
531 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
542 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
553 …che evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
564 …eback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[…
575 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
586 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
597 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
608 …ruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
619 …ide prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[…
630 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
641 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
652 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
663 …l cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
674 …ounts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[…
685 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
696 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
707 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
718 …ta cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
729 …requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[…
740 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
751 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
762 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
773 …mporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
784 …memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[…
795 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
806 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
817 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
828 …he prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
839 … reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[…
850 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
861 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
872 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
883 …he prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
894 …eline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[…
905 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
916 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
927 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
938 …L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
949 …r ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[…
960 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
971 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
982 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
993 …emory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
1004 … to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[…
1015 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
1026 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1037 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
1048 … instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
1059 …ache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[…
1070 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
1081 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1092 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…