Lines Matching +full:7 +full:- +full:1
4 "Counter": "0,1,2,3,4,5,6,7",
5 "CounterMask": "1",
6 "Deprecated": "1",
15 "Counter": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
19 …xecuting divide or square root operations. Accounts for integer and floating-point operations. Ava…
25 "Counter": "0,1,2,3,4,5,6,7",
26 "CounterMask": "1",
27 "Deprecated": "1",
36 "Counter": "0,1,2,3,4,5,6,7",
37 "CounterMask": "1",
46 "Counter": "0,1,2,3,4,5,6,7",
47 "CounterMask": "1",
48 "Deprecated": "1",
57 "Counter": "0,1,2,3,4,5,6,7",
66 "Counter": "0,1,2,3,4,5,6,7",
74 "Counter": "0,1,2,3,4,5,6,7",
83 "Counter": "0,1,2,3,4,5,6,7",
92 "Counter": "0,1,2,3,4,5,6,7",
101 "Counter": "0,1,2,3,4,5,6,7",
110 "Counter": "0,1,2,3,4,5,6,7",
119 "Counter": "0,1,2,3,4,5,6,7",
128 "Counter": "0,1,2,3,4,5,6,7",
137 "Counter": "0,1,2,3,4,5,6,7",
146 "Counter": "0,1,2,3,4,5,6,7",
154 "Counter": "0,1,2,3,4,5,6,7",
162 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
163 "Counter": "0,1,2,3,4,5,6,7",
172 "Counter": "0,1,2,3,4,5,6,7",
180 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
181 "Counter": "0,1,2,3,4,5,6,7",
184 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
190 "Counter": "0,1,2,3,4,5,6,7",
199 "Counter": "0,1,2,3,4,5,6,7",
208 "Counter": "0,1,2,3,4,5,6,7",
211 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
216 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
217 "Counter": "0,1,2,3,4,5,6,7",
220 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
225 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
226 "Counter": "0,1,2,3,4,5,6,7",
229 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
234 …"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 A…
235 "Counter": "0,1,2,3,4,5,6,7",
238 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optim…
244 "Counter": "0,1,2,3,4,5,6,7",
253 "Counter": "0,1,2,3,4,5,6,7",
262 "Counter": "0,1,2,3,4,5,6,7",
271 "Counter": "0,1,2,3,4,5,6,7",
272 "CounterMask": "1",
273 "EdgeDetect": "1",
282 "Counter": "0,1,2,3,4,5,6,7",
285 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
293 …1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counte…
299 "Counter": "0,1,2,3,4,5,6,7",
302 …1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counte…
308 "Counter": "Fixed counter 1",
316 "Counter": "0,1,2,3,4,5,6,7",
324 "Counter": "0,1,2,3",
334 "Counter": "0,1,2,3",
335 "CounterMask": "1",
344 "Counter": "0,1,2,3,4,5,6,7",
354 "Counter": "0,1,2,3",
364 "Counter": "0,1,2,3",
374 "Counter": "0,1,2,3,4,5,6,7",
384 "Counter": "0,1,2,3,4,5,6,7",
392 …"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was no…
393 "Counter": "0,1,2,3,4,5,6,7",
395 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
396 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
402 "Counter": "0,1,2,3,4,5,6,7",
411 "Counter": "0,1,2,3,4,5,6,7",
420 "Counter": "0,1,2,3,4,5,6,7",
429 "Counter": "0,1,2,3,4,5,6,7",
438 "Counter": "0,1,2,3,4,5,6,7",
448 "Counter": "0,1,2,3,4,5,6,7",
458 "Counter": "0,1,2,3,4,5,6,7",
467 "Counter": "0,1,2,3",
475 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
478 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
483 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
484 "Counter": "0,1,2,3,4,5,6,7",
487 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
492 "Counter": "0,1,2,3,4,5,6,7",
501 "Counter": "0,1,2,3,4,5,6,7",
509 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
518 "Counter": "0,1,2,3,4,5,6,7",
521 …ecified by the RCX register. Note the number of iterations is implementation-dependent. Available …
527 "Counter": "0,1,2,3,4,5,6,7",
528 "CounterMask": "1",
529 "EdgeDetect": "1",
538 "Counter": "0,1,2,3,4,5,6,7",
547 "Counter": "0,1,2,3,4,5,6,7",
556 "Counter": "0,1,2,3,4,5,6,7",
565 "Counter": "0,1,2,3,4,5,6,7",
576 "Counter": "0,1,2,3,4,5,6,7",
579 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
585 "Counter": "0,1,2,3,4,5,6,7",
594 "Counter": "0,1,2,3,4,5,6,7",
602 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
603 "Counter": "0,1,2,3,4,5,6,7",
606 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
611 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
612 "Counter": "0,1,2,3,4,5,6,7",
615 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
621 "Counter": "0,1,2,3,4,5,6,7",
630 "Counter": "0,1,2,3,4,5,6,7",
639 "Counter": "0,1,2,3,4,5,6,7",
648 "Counter": "0,1,2,3,4,5,6,7",
657 "Counter": "0,1,2,3",
666 "Counter": "0,1,2,3",
675 "Counter": "0,1,2,3",
684 "Counter": "0,1,2,3",
687 …"PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) a…
693 "Counter": "0,1,2,3,4,5,6,7",
694 "CounterMask": "1",
697 …ion": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector). Ava…
703 "Counter": "0,1,2,3,4,5,6,7",
707 …"Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector). Ava…
713 "Counter": "0,1,2,3,4,5,6,7",
716 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
722 "Counter": "0,1,2,3,4,5,6,7",
723 "CounterMask": "1",
724 "EdgeDetect": "1",
732 "BriefDescription": "Self-modifying code (SMC) detected.",
733 "Counter": "0,1,2,3,4,5,6,7",
736 …"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear. Ava…
742 "Counter": "0,1,2,3,4,5,6,7",
751 "Counter": "0,1,2,3,4,5,6,7",
760 "Counter": "0,1,2,3,4,5,6,7",
763 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
769 "Counter": "0,1,2,3,4,5,6,7",
778 "Counter": "0,1,2,3,4,5,6,7",
781 … This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch misp…
787 "Counter": "0,1,2,3,4,5,6,7",
788 "CounterMask": "1",
789 "EdgeDetect": "1",
792 "Invert": "1",
793 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
798 …iefDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end",
799 "Counter": "0,1,2,3,4,5,6,7",
802 …"Cycles when Reservation Station (RS) is empty due to a resource in the back-end Available PDIST c…
808 "Counter": "0,1,2,3,4,5,6,7",
809 "CounterMask": "1",
810 "Deprecated": "1",
811 "EdgeDetect": "1",
814 "Invert": "1",
821 "Counter": "0,1,2,3,4,5,6,7",
822 "Deprecated": "1",
830 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
831 "Counter": "0,1,2,3,4,5,6,7",
834 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
843 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
852 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
858 "Counter": "0,1,2,3,4,5,6,7",
866 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
869 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
874 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
875 "Counter": "0,1,2,3,4,5,6,7",
878 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
884 "Counter": "0,1,2,3",
893 "Counter": "0,1,2,3,4,5,6,7",
901 "BriefDescription": "Uops executed on port 1",
902 "Counter": "0,1,2,3,4,5,6,7",
905 … "PublicDescription": "Number of uops dispatch to execution port 1. Available PDIST counters: 0",
911 "Counter": "0,1,2,3,4,5,6,7",
920 "Counter": "0,1,2,3,4,5,6,7",
929 "Counter": "0,1,2,3,4,5,6,7",
938 "Counter": "0,1,2,3,4,5,6,7",
946 "BriefDescription": "Uops executed on ports 7 and 8",
947 "Counter": "0,1,2,3,4,5,6,7",
950 …"PublicDescription": "Number of uops dispatch to execution ports 7 and 8. Available PDIST counter…
956 "Counter": "0,1,2,3,4,5,6,7",
964 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
965 "Counter": "0,1,2,3,4,5,6,7",
966 "CounterMask": "1",
969 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
974 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
975 "Counter": "0,1,2,3,4,5,6,7",
979 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
984 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
985 "Counter": "0,1,2,3,4,5,6,7",
989 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
994 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
995 "Counter": "0,1,2,3,4,5,6,7",
999 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1004 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1005 "Counter": "0,1,2,3,4,5,6,7",
1006 "CounterMask": "1",
1009 …"PublicDescription": "Cycles where at least 1 uop was executed per-thread. Available PDIST counter…
1014 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1015 "Counter": "0,1,2,3,4,5,6,7",
1019 …"PublicDescription": "Cycles where at least 2 uops were executed per-thread. Available PDIST count…
1024 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1025 "Counter": "0,1,2,3,4,5,6,7",
1029 …"PublicDescription": "Cycles where at least 3 uops were executed per-thread. Available PDIST count…
1034 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1035 "Counter": "0,1,2,3,4,5,6,7",
1039 …"PublicDescription": "Cycles where at least 4 uops were executed per-thread. Available PDIST count…
1045 "Counter": "0,1,2,3,4,5,6,7",
1046 "CounterMask": "1",
1049 "Invert": "1",
1056 "Counter": "0,1,2,3,4,5,6,7",
1057 "CounterMask": "1",
1058 "Deprecated": "1",
1061 "Invert": "1",
1067 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1068 "Counter": "0,1,2,3,4,5,6,7",
1071 …"PublicDescription": "Counts the number of uops to be executed per-thread each cycle. Available PD…
1077 "Counter": "0,1,2,3,4,5,6,7",
1086 "Counter": "0,1,2,3,4,5,6,7",
1095 "Counter": "0,1,2,3,4,5,6,7",
1096 "CounterMask": "1",
1105 "Counter": "0,1,2,3,4,5,6,7",
1106 "CounterMask": "1",
1115 "Counter": "0,1,2,3,4,5,6,7",
1118 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1124 "Counter": "0,1,2,3,4,5,6,7",
1135 "Counter": "0,1,2,3,4,5,6,7",
1144 "Counter": "0,1,2,3,4,5,6,7",
1145 "CounterMask": "1",
1148 "Invert": "1",
1155 "Counter": "0,1,2,3,4,5,6,7",
1156 "CounterMask": "1",
1157 "Deprecated": "1",
1160 "Invert": "1",