Lines Matching +full:per +full:- +full:rate
3 "BriefDescription": "C1 residency percent per core",
4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
10 "BriefDescription": "C2 residency percent per package",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
17 "BriefDescription": "C6 residency percent per core",
18 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
24 "BriefDescription": "C6 residency percent per package",
25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
31 "BriefDescription": "Uncore frequency per die [GHZ]",
37 …"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instru…
270 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
283 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
324 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
338 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
343 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
349 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
354 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
358 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
365 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
370 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
373 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
378 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
381 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
386 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
389 … "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
394 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
397 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
398 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
405 …"MetricExpr": "100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_f…
409 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
412 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
417 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
421 …t_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (…
429 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
436 "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
437 …"MetricExpr": "100 - (tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottlene…
441 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
444 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
445 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
453 …"MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\…
458 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
467 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
471 … represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized…
479 … represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized…
488 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
492 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
497 …"MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES …
506 "MetricExpr": "max(0, tma_icache_misses - tma_code_l2_miss)",
521 …irst level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)",
522 "MetricExpr": "max(0, tma_itlb_misses - tma_code_stlb_miss)",
529 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
563 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
565 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
570 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
574 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
576 …MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L…
580 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
584 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
585 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
589 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
612 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
625 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
630 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCL…
634 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
638 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
643 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
652 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
667 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
678 …MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
683 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
688 "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequencer)",
692 …tiring instructions that that are decoder into two or more uops. This highly-correlates with the n…
696 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
701 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
710 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
714 …"BriefDescription": "This metric represents fraction of cycles where the Floating-Point Divider un…
722 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
727 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
731 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
736 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
740 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
745 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
749 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
754 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
758 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
763 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
769 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
774 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
778 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
783 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
787 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
789 …"MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
794 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
807 …ch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch…
811 …ch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch…
814 …scription": "Instructions per retired Mispredicts for conditional non-taken branches (lower number…
821 …Description": "Instructions per retired Mispredicts for conditional taken branches (lower number m…
828 …scription": "Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number …
835 …BriefDescription": "Instructions per retired Mispredicts for return branches (lower number means h…
842 …ion": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number mea…
855 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
856 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
862 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
867 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
870 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
875 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
878 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
883 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
892 "BriefDescription": "Fraction of branches that are non-taken conditionals",
905 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
911 …"MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_call…
922 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
928 "BriefDescription": "uops Executed per Cycle",
934 "BriefDescription": "Floating Point Operations Per Cycle",
940 …"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardle…
944 …per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-wi…
947 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
961 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
967 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
979 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
986 …Description": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number m…
992 "BriefDescription": "L2 cache true code cacheline misses per kilo instruction",
998 "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction",
1004 "BriefDescription": "Taken Branches retired Per Cycle",
1010 …"BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch d…
1014 …"PublicDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch …
1017 "BriefDescription": "Branch instructions per taken branch.",
1030 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
1035 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
1038 …riefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
1043 …blicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
1046 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
1051 …PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
1054 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
1059 …PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
1062 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
1067 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
1070 …fDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number mea…
1075 …cDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number mea…
1078 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
1083 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
1086 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
1093 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
1100 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
1107 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
1114 "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)",
1120 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
1127 …ion": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower …
1134 "BriefDescription": "Instructions per taken branch",
1139 …"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_…
1142 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1148 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1154 "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
1160 …"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evi…
1166 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1172 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1178 …iption": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that me…
1184 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1190 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
1196 …"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including spe…
1202 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1208 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
1209 "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
1214 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculati…
1220 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
1226 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (inc…
1232 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (inc…
1238 "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
1244 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1250 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1256 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
1286 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1292 "BriefDescription": "\"Bus lock\" per kilo instruction",
1298 "BriefDescription": "Off-core accesses per kilo instruction for modified write requests",
1304 …"BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculativ…
1310 …"BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative;…
1316 "BriefDescription": "Un-cacheable retired load per kilo instruction",
1322 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
1326 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1329 "BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses",
1336 …riefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- …
1340 …blicDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- …
1343 "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C)",
1347 …"PublicDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRA…
1350 "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C)",
1354 …"PublicDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand o…
1357 …ription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-s…
1363 …on": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-s…
1376 …n": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-s…
1388 "BriefDescription": "Average number of uops fetched from DSB per cycle",
1394 "BriefDescription": "Average number of uops fetched from MITE per cycle",
1400 "BriefDescription": "Instructions per a microcode Assist invocation",
1405 …tion": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower n…
1414 … "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
1421 …et unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized…
1453 "BriefDescription": "Giga Floating Point Operations Per Second",
1457 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
1474 …per Far Branch ( Far Branches apply upon transition from application to operating system, handling…
1481 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
1498 …to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches"
1520 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
1531 … "MetricExpr": "(power@energy\\-pkg@ * 61 + 15.6 * power@energy\\-ram@) / (duration_time * 1e6)",
1537 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_…
1567 …"BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data o…
1573 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1579 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
1585 "BriefDescription": "The ratio of Executed- by Issued-Uops",
1589 …ion": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. R…
1592 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
1598 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1604 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
1610 "BriefDescription": "Uops Per Instruction",
1617 "BriefDescription": "Uops per taken branch",
1625 "MetricExpr": "tma_divider - tma_fp_divider",
1641 …"BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neu…
1646 …"PublicDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Ne…
1650 …"BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector…
1655 …"PublicDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vecto…
1669 …"MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_thre…
1673 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
1678 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1682 … the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access…
1687 …"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_threa…
1706 …"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_thread…
1733 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1735 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
1740 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1753 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1754 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1761 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1803 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1813 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
1818 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1830 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1835 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
1839 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1840 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1844 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1850 …"MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
1855 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1868 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1895 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
1899 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
1903 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1908 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1912 …es in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequen…
1925 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
1930 …"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / …
1934 …lots where the CPU was retiring branch instructions that were not fused. Non-conditional branches …
1943 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
1947 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1948 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_opera…
1952 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1956 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
1957 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
1965 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
2008 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
2009 …)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O…
2013 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
2018 …0_PORTS + max(RS.EMPTY_RESOURCE - RESOURCE_STALLS.SCOREBOARD, 0)) / tma_info_thread_clks * (CYCLE_…
2022 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
2026 …metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execut…
2031 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
2035 …": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execut…
2041 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
2045 … metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execut…
2051 … metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execut…
2060 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
2069 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
2075 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
2080 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
2084 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
2089 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
2093 …sents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP o…
2098 …sents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP o…
2112 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
2117 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
2121 "BriefDescription": "This metric represents rate of split store accesses",
2126 …blicDescription": "This metric represents rate of split store accesses. Consider aligning your da…
2130 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
2135 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
2139 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
2144 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
2153 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
2158 …xpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
2162 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
2175 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
2176 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
2220 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…