Lines Matching +full:os +full:- +full:initiated
4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
18 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
76 …ved by the integrated I/O traffic controller (IIO) of IO reads that are initiated by end device co…
82 …ed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device co…
88 …"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are r…
94 …"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are r…
100 …"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are r…
106 …"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are …
112 …"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are …
118 …"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are …
124 …"BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controlle…
130 …"BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device contro…
136 …"BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the…
312 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
343 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
384 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
398 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
403 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
409 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
414 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
420 …"MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\…
425 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
434 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
438 … represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized…
446 … represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized…
455 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
459 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
464 …"MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES …
481 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
483 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
488 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
492 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
493 …MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L…
497 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
501 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
502 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
506 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
529 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
542 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
547 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCL…
551 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
555 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
560 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
569 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
584 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
595 …MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
600 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
605 "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequencer)",
609 …t are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the n…
613 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
618 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
627 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
631 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
636 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
640 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
645 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
649 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
654 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
658 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
663 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
667 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
672 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
678 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
683 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
687 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
692 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
696 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
698 …"MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
703 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
716 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
720 …"PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative …
723 …"BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lowe…
751 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
764 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
765 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
771 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
776 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
779 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
784 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
787 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
792 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
795 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
802 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
807 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
810 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
815 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
818 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
823 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
826 … "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
831 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
834 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
835 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
842 …"MetricExpr": "100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_f…
846 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
849 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
854 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
858 …_stores + tma_streaming_stores + tma_dtlb_store ) - tma_store_latency ) ) + tma_machine_clears * (…
866 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
873 "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
874 …"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tm…
878 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
881 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
882 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
894 "BriefDescription": "Fraction of branches that are non-taken conditionals",
907 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
913 …"MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_call…
924 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
942 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
946 …-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
949 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
963 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
969 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
981 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
1006 …"BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch d…
1010 …"PublicDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch …
1034 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
1039 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
1042 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
1047 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
1050 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
1055 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
1058 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
1063 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
1066 …"BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower numbe…
1071 …"PublicDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower numb…
1074 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
1079 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
1138 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1144 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1162 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1168 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1174 … instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
1180 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1198 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1205 "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
1240 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1246 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1282 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1294 "BriefDescription": "Off-core accesses per kilo instruction for modified write requests",
1300 …"BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculativ…
1306 …tion": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in…
1312 "BriefDescription": "Un-cacheable retired load per kilo instruction",
1318 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
1322 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1325 …riefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- …
1329 …blicDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- …
1332 "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C)",
1336 …"PublicDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRA…
1339 "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C)",
1343 …"PublicDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand o…
1346 … level TLB) code speculative misses per kilo instruction (misses of any page-size that complete th…
1352 …l TLB) data load speculative misses per kilo instruction (misses of any page-size that complete th…
1365 … TLB) data store speculative misses per kilo instruction (misses of any page-size that complete th…
1371 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
1403 … "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
1410 …et unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized…
1446 …egate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
1453 …isk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device co…
1460 …k) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device co…
1465 "MetricGroup": "Branches;OS",
1470 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
1472 "MetricGroup": "OS",
1476 "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
1478 "MetricGroup": "OS",
1487 …to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches"
1497 …"BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanose…
1501 …cy of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads …
1509 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
1525 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_…
1548 …"BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data o…
1554 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1566 "BriefDescription": "The ratio of Executed- by Issued-Uops",
1570 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
1579 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1585 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
1614 …"BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neu…
1619 …"PublicDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Ne…
1623 …"BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector…
1628 …"PublicDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vecto…
1642 …"MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_thre…
1646 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
1651 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1655 …e L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access…
1660 …"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_threa…
1669 …"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_thread…
1695 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1697 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
1702 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1715 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1716 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1723 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1741 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1751 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
1756 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1768 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1773 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
1777 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1778 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1782 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1788 …"MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
1793 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1806 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1833 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
1837 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
1841 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1846 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1855 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
1860 …"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / …
1864 …lots where the CPU was retiring branch instructions that were not fused. Non-conditional branches …
1873 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
1877 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1878 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_opera…
1882 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1886 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
1887 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
1895 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
1938 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1939 …)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O…
1943 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1948 …+ max(cpu@RS.EMPTY\\,umask\\=1@ - RESOURCE_STALLS.SCOREBOARD, 0)) / tma_info_thread_clks * (CYCLE_…
1952 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
1961 …-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
1971 …cal Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options…
1990 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
1999 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
2005 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
2010 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
2014 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
2019 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
2023 …sents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP o…
2028 …sents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP o…
2042 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
2047 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
2056 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
2060 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
2065 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
2069 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
2074 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
2083 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
2088 …xpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
2092 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
2105 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
2106 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
2126 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…
2149 "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
2156 "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
2163 "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",