Lines Matching +full:min +full:- +full:div

3 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
7 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
12 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
16 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
21 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
25 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
30 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
34 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
39 …-bit packed single and 256-bit packed double precision FP instructions retired; some instructions …
43 …-bit packed single precision and 256-bit packed double precision  floating-point instructions reti…
48 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
56 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
64 …-point instructions retired; some instructions will count twice as noted below. Each count represe…
68 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
73 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
77 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
82 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
86 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
91 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
121 …ssist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes onl…
130 …-code assist (numeric overflow/underflow) when the output value (destination register) is invalid.…
139 …"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operati…
148 …"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (n…
169 …   "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
174 …"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when …
179         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
184 …"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when …
189 …"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file…
193 …"PublicDescription": "This event counts the number of micro-operations cancelled after they were d…