Lines Matching +full:per +full:- +full:rate
3 "BriefDescription": "C2 residency percent per package",
4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
10 "BriefDescription": "C3 residency percent per core",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
17 "BriefDescription": "C3 residency percent per package",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
24 "BriefDescription": "C6 residency percent per core",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
31 "BriefDescription": "C6 residency percent per package",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
38 "BriefDescription": "C7 residency percent per core",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
45 "BriefDescription": "C7 residency percent per package",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
52 "BriefDescription": "Uncore frequency per die [GHZ]",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
96 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
102 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
107 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
112 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
117 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
128 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
137 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
143 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
147 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
170 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
172 "MetricExpr": "tma_backend_bound - tma_memory_bound",
177 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
181 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
187 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
202 …"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UO…
211 …"MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks…
224 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
233 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
237 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
242 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
257 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
272 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
276 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
281 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
285 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
290 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
294 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
299 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
303 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
308 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
312 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
317 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
327 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
331 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
337 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
350 …scription": "Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number …
357 …ion": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number mea…
370 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
376 "BriefDescription": "Floating Point Operations Per Cycle",
382 …"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardle…
386 …per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-wi…
389 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
403 …Description": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number m…
409 "BriefDescription": "Taken Branches retired Per Cycle",
415 "BriefDescription": "Branch instructions per taken branch.",
428 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
433 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
436 …riefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
441 …blicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
444 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
449 …PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
452 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
457 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
460 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
465 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
468 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
475 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
482 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
489 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
496 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
503 "BriefDescription": "Instructions per taken branch",
508 …"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_…
511 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
517 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
523 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
529 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
535 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
541 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
547 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
548 "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
553 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculati…
559 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
565 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (inc…
571 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (inc…
577 "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
583 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
589 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
613 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
620 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
625 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
672 "BriefDescription": "Giga Floating Point Operations Per Second",
676 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
679 …per Far Branch ( Far Branches apply upon transition from application to operating system, handling…
686 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
707 "MetricExpr": "power@energy\\-pkg@ * 61 / (tma_info_system_time * 1e6)",
713 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
737 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
743 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
749 "BriefDescription": "The ratio of Executed- by Issued-Uops",
753 …ion": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. R…
756 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
762 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
768 "BriefDescription": "Uops Per Instruction",
775 "BriefDescription": "Uops per taken branch",
792 …"MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thr…
796 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
801 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_…
838 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
839 "MetricExpr": "tma_retiring - tma_heavy_operations",
844 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
850 …HED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT…
870 "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
875 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
879 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
884 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
888 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
889 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
893 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
899 …CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS…
904 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
927 …"MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_cl…
931 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
940 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
962 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
970 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
978 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
983 …sents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Related metric…
1005 …ents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
1013 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1015 …- (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2…
1019 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1024 …ED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYC…
1028 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
1032 …metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execut…
1033 …_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECU…
1037 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
1041 …": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execut…
1042 …_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECU…
1046 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
1050 … metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execut…
1055 … metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execut…
1065 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
1069 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1075 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1079 "BriefDescription": "This metric represents rate of split store accesses",
1084 …blicDescription": "This metric represents rate of split store accesses. Consider aligning your da…
1088 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1093 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1097 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1102 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
1111 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1117 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STO…
1121 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
1135 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",