Lines Matching +full:3 +full:- +full:point

3 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
4         "Counter": "0,1,2,3",
7 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
12 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
13         "Counter": "0,1,2,3",
16 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
21 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
22         "Counter": "0,1,2,3",
25 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
30 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
31         "Counter": "0,1,2,3",
34 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
39 …"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed doub…
40         "Counter": "0,1,2,3",
43 …-bit packed single precision and 256-bit packed double precision  floating-point instructions reti…
48 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
49         "Counter": "0,1,2,3",
56 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
57         "Counter": "0,1,2,3",
64 …-point instructions retired; some instructions will count twice as noted below. Each count represe…
65         "Counter": "0,1,2,3",
68 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
73 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
74         "Counter": "0,1,2,3",
77 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
82 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
83         "Counter": "0,1,2,3",
86 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
91 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
92         "Counter": "0,1,2,3",
100         "Counter": "0,1,2,3",
108         "Counter": "0,1,2,3",
118         "Counter": "0,1,2,3",
121 …ssist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes onl…
127         "Counter": "0,1,2,3",
130 …point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination regis…
136         "Counter": "0,1,2,3",
139 …"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operati…
145         "Counter": "0,1,2,3",
148 …"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (n…
154         "Counter": "0,1,2,3",
162         "Counter": "0,1,2,3",
169 …   "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
170         "Counter": "0,1,2,3",
174 …"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when …
179         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
180         "Counter": "0,1,2,3",
184 …"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when …
189 …"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file…
190         "Counter": "0,1,2,3",
193 …"PublicDescription": "This event counts the number of micro-operations cancelled after they were d…