Lines Matching full:with

74 …stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
78 … Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
107 …cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
111 …stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
249 …ds with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in ME…
256 …ds with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in ME…
261 …ads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in ME…
268 …ads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in ME…
273 …ds with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in ME…
280 …ds with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in ME…
285 …ads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in ME…
292 …ads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in ME…
297 …ads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC…
304 …ads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC…
309 …ds with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in ME…
316 …ds with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in ME…
321 …ads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in ME…
328 …ads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in ME…
333 …ads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC…
340 …ads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC…
390 …"BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled…
395 …"PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enable…