Lines Matching +full:a +full:- +full:side

15 …che was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load"
20     "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
25 …escription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same No…
35 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on th…
45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin…
50     "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
60 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a …
65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi…
70 …on": "The processor's data cache was reloaded from a location other than the local core's L2 due t…
75 …n": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's…
95 …e was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load"
100 …scription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or…
110     "BriefDescription": "Threshold counter exceeded a value of 32"
115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…
130     "BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
135 …from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
140 …"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this t…
145 …iption": "A Page Table Entry was loaded into the TLB from a memory location including L4 from loca…
150 …A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L…
155 …"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the…
165 …A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on …
170     "BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
185 …Description": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different No…
200 …es to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
210 …A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on …
215 …ription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node …
220 …"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction…
225 …"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response fro…