Lines Matching +full:a +full:- +full:side
30 "BriefDescription": "IERAT reloaded (after a miss) for 4K pages"
45 …on": "The processor's data cache was reloaded from a location other than the local core's L3 due t…
50 …cription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's …
55 …"BriefDescription": "A Conditional Branch that resolved to taken was mispredicted as not taken (du…
60 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea…
65 "BriefDescription": "Read-write data cache collisions"
80 …"BriefDescription": "Cycles in which no new instructions can be dispatched to the ICT after a flus…
85 …"BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cac…
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to …
135 … ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that cont…
145 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load"
150 "BriefDescription": "Cycles when a tablewalk is pending on this thread on table 0"
190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie…
200 "BriefDescription": "Read-write data cache collisions"
205 … to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
225 …cles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load"
230 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load"
240 "BriefDescription": "A hwsync instruction was decoded and transferred"
255 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load"
265 … "BriefDescription": "Any port snooper hit L3. Up to 4 can happen in a cycle but we only count 1"
280 …a double-word boundary, which causes it to require an additional slice than than what normally wou…
285 "BriefDescription": "A sync is in the S2Q (edge detect to count)"
290 "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet"
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
305 …"BriefDescription": "If a load that has already returned data and has to relaunch for any reason t…
320 …e was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load"
350 …s to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load"
385 … shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to …
395 …a double-word boundary, which causes it to require an additional slice than than what normally wou…
405 …"BriefDescription": "TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified…
425 "BriefDescription": "A data line was written to the L1 due to a hardware or software prefetch"
430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
435 …ocessor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load"
445 "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt"
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
455 "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
465 …"BriefDescription": "A load-hit-load condition with Strong Address Ordering will have address comp…
470 …-form branch was mispredicted due to the predicted target address missing from EAT. The EAT force…
475 …a double-word boundary, which causes it to require an additional slice than than what normally wou…
480 …a double-word boundary, which causes it to require an additional slice than than what normally wou…
490 …"BriefDescription": "BTAC predicts a taken branch and the BHT agrees, and the target address is co…
495 …ion": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load"
500 "BriefDescription": "TM Store (fav or non-fav) ran into conflict (failed)"
510 …cription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2…
515 …anch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-for…
520 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea…
550 …umber of load instructions that finished with an L1 miss. Note that even if a load spans multiple …
565 …from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load"
575 …"BriefDescription": "Finish stall because the NTF instruction was a store that was held in LSAQ be…
580 …"Conditional Branch Completed that had its target address predicted. Only XL-form branches set thi…
605 …"BriefDescription": "A demand load referenced a line in an active prefetch stream. The stream coul…
630 …ocessor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load"
640 …n": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load"
645 …"BriefDescription": "Number of times a load or store instruction was unable to launch/relaunch bec…
650 …"BriefDescription": "Reloading line was brought in private for a specific thread. Most lines are …
655 "BriefDescription": "Non-TM Load caused any thread to fail"
660 …-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons …
685 …"BriefDescription": "L3 load prefetch, sourced from a hardware or software stream, was sent to the…
705 …"BriefDescription": "All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this t…
710 …a double-word boundary, which causes it to require an additional slice than than what normally wou…
720 …ption": "Any port snooper detects a store to a line in the Sx state and invalidates the line. Up …
730 "BriefDescription": "32-bit constant generation"
735 …e was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load"
765 …"BriefDescription": "Total number of taken branches that were incorrectly predicted as not-taken. …
810 …efDescription": "Duration in cycles to reload from a location other than the local core's L2 due t…
825 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre…
830 …"BriefDescription": "L3 load prefetch, sourced from a software prefetch stream, was sent to the ne…
840 …s reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
845 …-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an addre…
860 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the cor…
870 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked …
875 "BriefDescription": "Transaction failed because there was a TLBIE hit in the bloom filter"
890 …a double-word boundary, which causes it to require an additional slice than than what normally wou…
900 …"BriefDescription": "The LSU requested a line from L2 for translation. It may be satisfied from a…
905 …ription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load"
910 …cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load"
930 "BriefDescription": "L2 Squashed a demand or prefetch request"
945 …a trigger from the dbg macros. These actions include things like flushing the next op encountered …
975 "BriefDescription": "IERAT Reloaded (Miss) for a 64k page"
985 "BriefDescription": "Snoop dispatched for a read and was M (true M)"
990 "BriefDescription": "Marked store had to do a bkill"
1000 …tall because the NTF instruction was a load that was held in LSAQ (load-store address queue) becau…
1005 …n Mep state (includes casthrough to memory). The Mepf state indicates that a line was brought in …
1015 …ified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip d…
1035 …"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand…
1055 …A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L…
1060 …uration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a…
1080 "BriefDescription": "L2 Castouts - Modified (M,Mu,Me)"
1085 …"BriefDescription": "Number of times a load or store instruction was unable to launch/relaunch bec…
1090 …"BriefDescription": "A larx is flushed because an older larx has an LMQ reservation for the same t…
1095 …"BriefDescription": "Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalida…
1125 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
1135 …"BriefDescription": "L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip…
1140 … ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that cont…
1145 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
1155 …: "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cac…
1160 …-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision …
1180 … processor's data cache was reloaded from a memory location including L4 from local remote or dist…
1195 …n": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load"
1200 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load"
1205 …cles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load"
1210 …he was reloaded either shared or modified data from another core's L2/L3 on a different chip (remo…
1215 …a self-induced conflict occurred in Suspended state, due to one of the following: a store to a sto…
1225 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1230 …nstructions finished. This includes instructions in the speculative path of a branch that may be f…
1250 …data comes in for an D-side fetch where data came EXCLUSIVELY from memory that was for hpc_read64,…
1265 …a double-word boundary, which causes it to require an additional slice than than what normally wou…
1275 …"BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EX…
1290 "BriefDescription": "L2 Castouts - Shared (Tx,Sx)"
1295 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1300 "BriefDescription": "All successful D-Side Load dispatches that were an L2 miss for this thread"
1305 …e was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load"
1315 …cles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load"
1320 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due t…
1325 "BriefDescription": "Instruction SLB Miss - Total of all segment sizes"
1345 … the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it …
1355 "BriefDescription": "Non-TM Store caused any thread to fail"
1365 "BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt"
1370 …"BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) fo…
1380 …o the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
1385 …aken but it is either predicted not-taken by the BHT, or the target address is wrong (less common)…
1390 … ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that cont…
1405 "BriefDescription": "All D-side store dispatch attempts for this thread"
1410 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to reason …
1415 …"BriefDescription": "A demand load referenced a line in an active strided prefetch stream. The str…
1425 "BriefDescription": "Threshold counter exceeded a value of 512"
1430 …"BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatche…
1435 …ription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node o…
1440 "BriefDescription": "Read-write data cache collisions"
1445 "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread"
1480 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
1495 …The processor's data cache was reloaded from local core's L3 without conflict due to a marked load"
1500 …"BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) fo…
1505 …"BriefDescription": "Valid when first beat of data comes in for an I-side fetch where data came fr…
1510 "BriefDescription": "Read-write data cache collisions"
1525 …The processor's data cache was reloaded from local core's L2 without conflict due to a marked load"
1530 …"BriefDescription": "Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared s…
1540 "BriefDescription": "32-bit displacement D-form and 16-bit displacement X-form"
1545 … to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load"
1555 …d. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
1560 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
1570 …BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch …
1580 …s reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load"
1590 … ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that cont…
1595 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre…
1615 …"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the …
1630 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
1635 …"BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed du…
1645 …"BriefDescription": "Cycles in which 8 or less Issue Queue entries are in use. This is a shared ev…
1650 …"BriefDescription": "Marked branch instruction completed with a target address less than current i…
1675 …"BriefDescription": "TM aborted because a conflict occurred with a non-transactional access by ano…
1685 …ription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node …
1690 "BriefDescription": "A demand miss collides with a prefetch for the same line"
1705 …cription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch c…
1710 …r's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a…
1715 …"BriefDescription": "I-side L2 MRU touch sent to L2 for this thread I-side L2 MRU touch commands s…
1720 "BriefDescription": "Store-Hit-Load Table Entry Created"
1740 "BriefDescription": "L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)"
1750 …"BriefDescription": "A ptesync instruction was counted when the instruction is decoded and transmi…
1755 …"BriefDescription": "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM…
1770 …"BriefDescription": "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it w…
1775 "BriefDescription": "TM aborted because a conflict occurred with another transaction."
1780 "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled"
1785 "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits"
1805 … "BriefDescription": "All successful D-Side Store dispatches that were an L2 miss for this thread"
1815 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a …
1845 …on": "The processor's data cache was reloaded from a location other than the local core's L2 due t…
1850 "BriefDescription": "TM Store (fav or non-fav) caused another thread to fail"
1895 …fDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node…
1900 …ified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip d…
1905 …fDescription": "The instruction was flushed because of a sequential load/store consistency. If a …
1915 …hared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip d…
1935 "BriefDescription": "Cycles when a tablewalk is pending on this thread on table 1"
1940 "BriefDescription": "cycles L2 RC took for a bkill"
1945 …ription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load"
1950 …scription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or…
1955 …escription": "L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)"
1960 …"BriefDescription": "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due …
1970 …tion": "Duration in cycles to reload from a memory location including L4 from local remote or dist…
1990 "BriefDescription": "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)"
2010 …cription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3…
2020 …a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cas…
2030 …"BriefDescription": "Quad-word loads (lq) are considered atomic because they always span at least …
2035 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
2055 … shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to …
2060 …ption": "A Page Table Entry was loaded into the TLB either shared or modified data from another co…
2065 …"BriefDescription": "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pul…
2075 …a double-word boundary, which causes it to require an additional slice than than what normally wou…
2085 …castout of line that was StoreCopy (original value of speculatively written line) in a Transaction"
2095 … "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread"
2110 …escription": "The LSU detects the condition that a stcx instruction failed. No requirement to wait…
2120 "BriefDescription": "Nested or not nested tend failed for a marked tend instruction"
2135 …"BriefDescription": "Any port snooper L3 miss or collision. Up to 4 can happen in a cycle but we …
2140 …"BriefDescription": "L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group…
2150 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
2200 "BriefDescription": "All successful D-side store dispatches for this thread"
2205 …"BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatche…
2220 …e was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load"
2225 … "BriefDescription": "Total L3 COs occurred on LCO L3.1 (good cresp, may end up in mem on a retry)"
2240 "BriefDescription": "All successful D-side store dispatches for this thread (L2 miss + L2 hits)"
2260 … "BriefDescription": "CLB (control logic block - indicates quadword fetch block) Hold: Any Reason"
2275 … unit determines whether the tbegin instruction is outer or nested. This is a speculative count, w…
2310 …"BriefDescription": "Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0…
2325 …"BriefDescription": "Fetching is stopped due to an incoming instruction that will result in a flus…
2330 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to address…