Lines Matching full:fetches

1235 …al and Final Pump Scope was chip pump (prediction=correct) for instruction fetches and prefetches",
1241 …L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches",
1247 …L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches",
1253 …nother chip's L4 on a different Node or Group (Distant) due to instruction fetches and prefetches",
1259 …other chip's memory on the same Node or Group (Distant) due to instruction fetches and prefetches",
1265 …r's Instruction cache was reloaded from local core's L2 due to instruction fetches and prefetches",
1271 …dified (M) data from another core's L2 on the same chip due to instruction fetches and prefetches",
1277 …Shared (S) data from another core's L2 on the same chip due to instruction fetches and prefetches",
1283 …reloaded from a location other than the local core's L2 due to instruction fetches and prefetches",
1289 …oaded from local core's L2 with load hit store conflict due to instruction fetches and prefetches",
1295 …as reloaded from local core's L2 with dispatch conflict due to instruction fetches and prefetches",
1301 …core's L2 hit without dispatch conflicts on Mepf state. due to instruction fetches and prefetches",
1307 …ache was reloaded from local core's L2 without conflict due to instruction fetches and prefetches",
1313 …r's Instruction cache was reloaded from local core's L3 due to instruction fetches and prefetches",
1319 …ed (M) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches",
1325 …ed (S) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches",
1331 …dified (M) data from another core's L3 on the same chip due to instruction fetches and prefetches",
1337 …Shared (S) data from another core's L3 on the same chip due to instruction fetches and prefetches",
1349 …as reloaded from local core's L3 with dispatch conflict due to instruction fetches and prefetches",
1355 …core's L3 without dispatch conflicts hit on Mepf state. due to instruction fetches and prefetches",
1361 …ache was reloaded from local core's L3 without conflict due to instruction fetches and prefetches",
1367 …ction cache was reloaded from the local chip's L4 cache due to instruction fetches and prefetches",
1373 …ruction cache was reloaded from the local chip's Memory due to instruction fetches and prefetches",
1379 …mory location including L4 from local remote or distant due to instruction fetches and prefetches",
1385 …er core's L2/L3 on a different chip (remote or distant) due to instruction fetches and prefetches",
1391 …odified data from another core's L2/L3 on the same chip due to instruction fetches and prefetches",
1397 … or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches",
1403 … or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches",
1409 …m another chip's L4 on the same Node or Group ( Remote) due to instruction fetches and prefetches",
1415 …other chip's memory on the same Node or Group ( Remote) due to instruction fetches and prefetches",
1421 …l and Final Pump Scope was group pump (prediction=correct) for instruction fetches and prefetches",
1427 … ended up either larger or smaller than Initial Pump Scope for instruction fetches and prefetches",
1433 …ope (Group) ended up larger than Initial Pump Scope (Chip) for instruction fetches and prefetches",
1439 …"Pump prediction correct. Counts across all types of pumps for instruction fetches and prefetches",
1445 …on": "Pump misprediction. Counts across all types of pumps for instruction fetches and prefetches",
1451 … and Final Pump Scope was system pump (prediction=correct) for instruction fetches and prefetches",
1457 …l scope was System and it should have been smaller. Counts for instruction fetches and prefetches",
1463 …stem) ended up larger than Initial Pump Scope (Chip/Group) for instruction fetches and prefetches",
1469     "BriefDescription": "Instruction fetches from L1",