Lines Matching full:ls1
317 … "Completion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data fini…
647 …located through the hardware prefetch mechanism or through software. This is combined ls0 and ls1",
1601 "BriefDescription": "LS1 ISU reject",
1895 "BriefDescription": "LS1 L1 D cache load references counted at finish, gated by reject",
1896 …"PublicDescription": "LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D c…
1943 "BriefDescription": "LS1 Erat miss due to prefetch",
1944 "PublicDescription": "LS1 Erat miss due to prefetch42"
1949 "BriefDescription": "LS1 L1 cache data prefetches",
1950 "PublicDescription": "LS1 L1 cache data prefetches42"
2051 "BriefDescription": "LS1 Flush: LRQ",
2052 "PublicDescription": "LS1 Flush: LRQLSU1 LRQ flushes"
2057 "BriefDescription": "LS1 Flush: SRQ",
2058 "PublicDescription": "LS1 Flush: SRQLSU1 SRQ lhs flushes"
2069 "BriefDescription": "LS1 Flush: Unaligned Store",
2070 "PublicDescription": "LS1 Flush: Unaligned StoreLSU1 unaligned store flushes"
2075 "BriefDescription": "ls1 l1 tm cam cancel",
2076 "PublicDescription": "ls1 l1 tm cam cancel42"
2087 "BriefDescription": "LS1 Load Merge with another cacheline request",
2088 "PublicDescription": "LS1 Load Merge with another cacheline request42"
2093 "BriefDescription": "LS1 Non-cachable Loads counted at finish",
2094 "PublicDescription": "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads"
2111 "BriefDescription": "LS1 SRQ forwarded data to a load",
2112 "PublicDescription": "LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded"
2117 "BriefDescription": "ls1 store reject",
2118 "PublicDescription": "ls1 store reject42"
2261 "BriefDescription": "LS1 Vector Loads",
2262 "PublicDescription": "LS1 Vector Loads42"
2267 "BriefDescription": "LS1 Load Merge with another cacheline request",
2268 "PublicDescription": "LS1 Load Merge with another cacheline request42"
2411 "BriefDescription": "count at finish so can return only on ls0 or ls1",