Lines Matching full:of
8 …ion": "This metric is the percentage of cycles that were stalled due to resource constraints in th…
10 "ScaleUnit": "1percent of cycles"
19 … the ratio of branches mispredicted to the total number of branches architecturally executed. This…
26 …"BriefDescription": "This metric measures the number of branch mispredictions per thousand instruc…
33 …"BriefDescription": "This metric measures branch operations as a percentage of operations speculat…
35 "ScaleUnit": "1percent of operations"
40 …"BriefDescription": "This metric measures crypto operations as a percentage of operations speculat…
42 "ScaleUnit": "1percent of operations"
47 …"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions e…
54 …ic measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an in…
65 …ion": "This metric is the percentage of cycles that were stalled due to resource constraints in th…
67 "ScaleUnit": "1percent of cycles"
72 …"BriefDescription": "This metric measures scalar integer operations as a percentage of operations …
74 "ScaleUnit": "1percent of operations"
79 "BriefDescription": "This metric measures the number of instructions retired per cycle.",
86 …"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instruc…
93 …ures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This give…
100 … ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. T…
107 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
114 …he ratio of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. Thi…
121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
128 …of level 1 instruction cache accesses missed to the total number of level 1 instruction cache acce…
135 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
142 …o of level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB access…
149 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
156 …s the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This g…
163 …"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per …
170 …ratio of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. …
177 …"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per th…
184 …o of last level cache read accesses hit in the cache to the total number of last level cache acces…
191 … ratio of last level cache read accesses missed to the total number of last level cache accesses. …
198 …"BriefDescription": "This metric measures the number of last level cache read accesses missed per …
205 …"BriefDescription": "This metric measures load operations as a percentage of operations speculativ…
207 "ScaleUnit": "1percent of operations"
215 …n": "This metric measures scalar floating point operations as a percentage of operations speculati…
217 "ScaleUnit": "1percent of operations"
222 …"BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operat…
224 "ScaleUnit": "1percent of operations"
229 …"BriefDescription": "This metric measures store operations as a percentage of operations speculati…
231 "ScaleUnit": "1percent of operations"