Lines Matching full:sample

26 On Arm64 this uses SPE to sample load and store operations, therefore hardware
31 On AMD this use IBS Op PMU to sample load-store operations.
49 	Record/Report sample physical addresses
52 	Record/Report sample data address page size
97 	one sample per line.
106 	- symbol_daddr: name of data symbol being executed on at the time of sample
107 	- symbol_iaddr: name of code symbol being executed on at the time of sample
109 	             on at the time of the sample
110 	- locked: whether the bus was locked at the time of the sample
111 	- tlb: type of tlb access for the data at the time of the sample
112 	- mem: type of memory access for the data at the time of the sample
113 	- snoop: type of snoop (if any) for the data at the time of the sample
114 	- dcacheline: the cacheline the data address is on at the time of the sample
115 	- phys_daddr: physical address of data being executed on at the time of sample
116 	- data_page_size: the data page size of data being executed on at the time of sample
117 	- blocked: reason of blocked load access for the data at the time of the sample
128 	following fields to break down sample periods.
130 	- op: operation in the sample instruction (load, store, prefetch, ...)
131 	- cache: location in CPU cache (L1, L2, ...) where the sample hit
132 	- mem: location in memory or other places the sample hit
133 	- dtlb: location in Data TLB (L1, L2) where the sample hit
159 sample period, perf-mem overhead is calculated using sample weight. E.g.
160 there are two samples in perf.data file, both with the same sample period,
161 but one sample with weight 180 and the other with weight 20:
178 information in the sample.  Some of them have the same name with the existing