Lines Matching +full:mod +full:- +full:12 +full:b
1 // SPDX-License-Identifier: GPL-2.0-or-later
38 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
41 ({ t r = get_unaligned((t *)(insn)->next_byte); (insn)->next_byte += sizeof(t); leXX_to_cpu(t, r); })
44 ({ t r = get_unaligned((t *)(insn)->next_byte + n); leXX_to_cpu(t, r); })
55 * insn_init() - initialize struct insn
59 * @x86_64: !0 for 64-bit kernel or 64-bit app
71 insn->kaddr = kaddr;
72 insn->end_kaddr = kaddr + buf_len;
73 insn->next_byte = kaddr;
74 insn->x86_64 = x86_64;
75 insn->opnd_bytes = 4;
77 insn->addr_bytes = 8;
79 insn->addr_bytes = 4;
95 insn->emulate_prefix_size = len;
96 insn->next_byte += len;
113 * insn_get_prefixes - scan x86 instruction prefix bytes
116 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte
117 * to point to the (first) opcode. No effect if @insn->prefixes.got
126 struct insn_field *prefixes = &insn->prefixes;
128 insn_byte_t b, lb;
131 if (prefixes->got)
138 b = peek_next(insn_byte_t, insn);
139 attr = inat_get_opcode_attribute(b);
143 if (prefixes->bytes[i] == b)
148 prefixes->bytes[nb++] = b;
151 if (insn->x86_64)
152 insn->addr_bytes ^= 12;
154 insn->addr_bytes ^= 6;
157 insn->opnd_bytes ^= 6;
160 prefixes->nbytes++;
161 insn->next_byte++;
162 lb = b;
163 b = peek_next(insn_byte_t, insn);
164 attr = inat_get_opcode_attribute(b);
167 if (lb && lb != insn->prefixes.bytes[3]) {
168 if (unlikely(insn->prefixes.bytes[3])) {
170 b = insn->prefixes.bytes[3];
172 if (prefixes->bytes[i] == lb)
173 insn_set_byte(prefixes, i, b);
175 insn_set_byte(&insn->prefixes, 3, lb);
179 if (insn->x86_64) {
180 b = peek_next(insn_byte_t, insn);
181 attr = inat_get_opcode_attribute(b);
183 insn_field_set(&insn->rex_prefix, b, 1);
184 insn->next_byte++;
185 if (X86_REX_W(b))
187 insn->opnd_bytes = 8;
189 insn_set_byte(&insn->rex_prefix, 0, b);
190 b = peek_nbyte_next(insn_byte_t, insn, 1);
191 insn_set_byte(&insn->rex_prefix, 1, b);
192 insn->rex_prefix.nbytes = 2;
193 insn->next_byte += 2;
194 if (X86_REX_W(b))
196 insn->opnd_bytes = 8;
197 insn->rex_prefix.got = 1;
201 insn->rex_prefix.got = 1;
204 b = peek_next(insn_byte_t, insn);
205 attr = inat_get_opcode_attribute(b);
208 if (!insn->x86_64) {
210 * In 32-bits mode, if the [7:6] bits (mod bits of
211 * ModRM) on the second byte are not 11b, it is
217 insn_set_byte(&insn->vex_prefix, 0, b);
218 insn_set_byte(&insn->vex_prefix, 1, b2);
221 insn_set_byte(&insn->vex_prefix, 2, b2);
223 insn_set_byte(&insn->vex_prefix, 3, b2);
224 insn->vex_prefix.nbytes = 4;
225 insn->next_byte += 4;
226 if (insn->x86_64 && X86_VEX_W(b2))
228 insn->opnd_bytes = 8;
231 insn_set_byte(&insn->vex_prefix, 2, b2);
232 insn->vex_prefix.nbytes = 3;
233 insn->next_byte += 3;
234 if (insn->x86_64 && X86_VEX_W(b2))
236 insn->opnd_bytes = 8;
239 * For VEX2, fake VEX3-like byte#2.
243 insn_set_byte(&insn->vex_prefix, 2, b2 & 0x7f);
244 insn->vex_prefix.nbytes = 2;
245 insn->next_byte += 2;
249 insn->vex_prefix.got = 1;
251 prefixes->got = 1;
256 return -ENODATA;
260 * insn_get_opcode - collect opcode(s)
263 * Populates @insn->opcode, updates @insn->next_byte to point past the
264 * opcode byte(s), and set @insn->attr (except for groups).
266 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
275 struct insn_field *opcode = &insn->opcode;
279 if (opcode->got)
289 opcode->nbytes = 1;
296 insn->attr = inat_get_avx_attribute(op, m, p);
298 if (inat_evex_scalable(insn->attr) && !insn_vex_w_bit(insn) &&
300 insn->opnd_bytes = 2;
301 if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) ||
302 (!inat_accept_vex(insn->attr) &&
303 !inat_is_group(insn->attr))) {
305 insn->attr = 0;
306 return -EINVAL;
319 insn->attr = inat_get_escape_attribute(op, pfx_id, esc_attr);
321 insn->attr = inat_get_opcode_attribute(op);
326 insn->attr = inat_get_opcode_attribute(op);
327 if (insn->x86_64 && inat_is_invalid64(insn->attr)) {
329 insn->attr &= INAT_INV64;
332 while (inat_is_escape(insn->attr)) {
335 opcode->bytes[opcode->nbytes++] = op;
337 insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr);
340 if (inat_must_vex(insn->attr)) {
342 insn->attr = 0;
343 return -EINVAL;
347 opcode->got = 1;
351 return -ENODATA;
355 * insn_get_modrm - collect ModRM byte, if any
358 * Populates @insn->modrm and updates @insn->next_byte to point past the
360 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
368 struct insn_field *modrm = &insn->modrm;
369 insn_byte_t pfx_id, mod;
372 if (modrm->got)
379 if (inat_has_modrm(insn->attr)) {
380 mod = get_next(insn_byte_t, insn);
381 insn_field_set(modrm, mod, 1);
382 if (inat_is_group(insn->attr)) {
384 insn->attr = inat_get_group_attribute(mod, pfx_id,
385 insn->attr);
386 if (insn_is_avx(insn) && !inat_accept_vex(insn->attr)) {
388 insn->attr = 0;
389 return -EINVAL;
394 if (insn->x86_64 && inat_is_force64(insn->attr))
395 insn->opnd_bytes = 8;
397 modrm->got = 1;
401 return -ENODATA;
406 * insn_rip_relative() - Does instruction use RIP-relative addressing mode?
410 * ModRM byte. No effect if @insn->x86_64 is 0.
414 struct insn_field *modrm = &insn->modrm;
417 if (!insn->x86_64)
424 * For rip-relative instructions, the mod field (top 2 bits)
427 return (modrm->nbytes && (modrm->bytes[0] & 0xc7) == 0x5);
431 * insn_get_sib() - Get the SIB byte of instruction
446 if (insn->sib.got)
453 if (insn->modrm.nbytes) {
454 modrm = insn->modrm.bytes[0];
455 if (insn->addr_bytes != 2 &&
457 insn_field_set(&insn->sib,
461 insn->sib.got = 1;
466 return -ENODATA;
471 * insn_get_displacement() - Get the displacement of instruction
476 * Displacement value is sign-expanded.
484 insn_byte_t mod, rm, base;
487 if (insn->displacement.got)
494 if (insn->modrm.nbytes) {
497 * mod = 00 - no displacement fields (exceptions below)
498 * mod = 01 - 1-byte displacement field
499 * mod = 10 - displacement field is 4 bytes, or 2 bytes if
500 * address size = 2 (0x67 prefix in 32-bit mode)
501 * mod = 11 - no memory operand
504 * mod = 00, r/m = 110 - displacement field is 2 bytes
507 * mod != 11, r/m = 100 - SIB byte exists
508 * mod = 00, SIB base = 101 - displacement field is 4 bytes
509 * mod = 00, r/m = 101 - rip-relative addressing, displacement
512 mod = X86_MODRM_MOD(insn->modrm.value);
513 rm = X86_MODRM_RM(insn->modrm.value);
514 base = X86_SIB_BASE(insn->sib.value);
515 if (mod == 3)
517 if (mod == 1) {
518 insn_field_set(&insn->displacement,
520 } else if (insn->addr_bytes == 2) {
521 if ((mod == 0 && rm == 6) || mod == 2) {
522 insn_field_set(&insn->displacement,
526 if ((mod == 0 && rm == 5) || mod == 2 ||
527 (mod == 0 && base == 5)) {
528 insn_field_set(&insn->displacement,
534 insn->displacement.got = 1;
538 return -ENODATA;
544 switch (insn->addr_bytes) {
546 insn_field_set(&insn->moffset1, get_next(short, insn), 2);
549 insn_field_set(&insn->moffset1, get_next(int, insn), 4);
552 insn_field_set(&insn->moffset1, get_next(int, insn), 4);
553 insn_field_set(&insn->moffset2, get_next(int, insn), 4);
558 insn->moffset1.got = insn->moffset2.got = 1;
569 switch (insn->opnd_bytes) {
571 insn_field_set(&insn->immediate, get_next(short, insn), 2);
575 insn_field_set(&insn->immediate, get_next(int, insn), 4);
590 switch (insn->opnd_bytes) {
592 insn_field_set(&insn->immediate1, get_next(short, insn), 2);
595 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
596 insn->immediate1.nbytes = 4;
599 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
600 insn_field_set(&insn->immediate2, get_next(int, insn), 4);
605 insn->immediate1.got = insn->immediate2.got = 1;
615 switch (insn->opnd_bytes) {
617 insn_field_set(&insn->immediate1, get_next(short, insn), 2);
620 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
628 insn_field_set(&insn->immediate2, get_next(unsigned short, insn), 2);
629 insn->immediate1.got = insn->immediate2.got = 1;
637 * insn_get_immediate() - Get the immediate in an instruction
642 * Basically, most of immediates are sign-expanded. Unsigned-value can be
643 * computed by bit masking with ((1 << (nbytes * 8)) - 1)
653 if (insn->immediate.got)
660 if (inat_has_moffset(insn->attr)) {
666 if (!inat_has_immediate(insn->attr))
669 switch (inat_immediate_size(insn->attr)) {
671 insn_field_set(&insn->immediate, get_next(signed char, insn), 1);
674 insn_field_set(&insn->immediate, get_next(short, insn), 2);
677 insn_field_set(&insn->immediate, get_next(int, insn), 4);
680 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
681 insn_field_set(&insn->immediate2, get_next(int, insn), 4);
699 if (inat_has_second_immediate(insn->attr)) {
700 insn_field_set(&insn->immediate2, get_next(signed char, insn), 1);
703 insn->immediate.got = 1;
707 return -ENODATA;
711 * insn_get_length() - Get the length of instruction
718 * - 0 on success
719 * - < 0 on error
725 if (insn->length)
732 insn->length = (unsigned char)((unsigned long)insn->next_byte
733 - (unsigned long)insn->kaddr);
741 return insn->opcode.got && insn->modrm.got && insn->sib.got &&
742 insn->displacement.got && insn->immediate.got;
746 * insn_decode() - Decode an x86 instruction
760 #define INSN_MODE_KERN (enum insn_mode)-1 /* __ignore_sync_check__ mode is only valid in the kernel */
774 return -EINVAL;