Lines Matching refs:edx
18 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
64 1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)
65 1, 0, edx, 1, vme , Virtual-8086 Mode Extensions
66 1, 0, edx, 2, de , Debugging Extensions
67 1, 0, edx, 3, pse , Page Size Extension
68 1, 0, edx, 4, tsc , Time Stamp Counter
69 …1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR…
70 1, 0, edx, 6, pae , Physical Address Extensions
71 1, 0, edx, 7, mce , Machine Check Exception
72 1, 0, edx, 8, cx8 , CMPXCHG8B instruction
73 1, 0, edx, 9, apic , APIC on-chip
74 … 1, 0, edx, 11, sep , SYSENTER, SYSEXIT, and associated MSRs
75 1, 0, edx, 12, mtrr , Memory Type Range Registers
76 1, 0, edx, 13, pge , Page Global Extensions
77 1, 0, edx, 14, mca , Machine Check Architecture
78 1, 0, edx, 15, cmov , Conditional Move Instruction
79 1, 0, edx, 16, pat , Page Attribute Table
80 1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
81 1, 0, edx, 18, pn , Processor Serial Number
82 1, 0, edx, 19, clflush , CLFLUSH instruction
83 1, 0, edx, 21, dts , Debug Store
84 1, 0, edx, 22, acpi , Thermal monitor and clock control
85 1, 0, edx, 23, mmx , MMX instructions
86 1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions
87 1, 0, edx, 25, sse , SSE instructions
88 1, 0, edx, 26, sse2 , SSE2 instructions
89 1, 0, edx, 27, ss , Self Snoop
90 1, 0, edx, 28, ht , Hyper-threading
91 1, 0, edx, 29, tm , Thermal Monitor
92 …1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now r…
93 1, 0, edx, 31, pbe , Pending Break Enable
113 2, 0, edx, 7:0, desc12 , Descriptor #12
114 2, 0, edx, 15:8, desc13 , Descriptor #13
115 2, 0, edx, 23:16, desc14 , Descriptor #14
116 2, 0, edx, 30:24, desc15 , Descriptor #15
117 … 2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
132 …4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Low…
133 … 4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
134 …4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex functi…
143 …5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using…
144 …5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using…
145 …5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using…
146 …5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using…
147 …5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using…
148 …5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using…
149 …5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using…
150 …5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using…
180 6, 0, edx, 0, perfcap_reporting , Performance capability reporting
181 … 6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
182 …6, 0, edx, 11:8, feedback_sz , HW feedback interface struct size, in 4K …
183 …6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU index @ HW feedback stru…
246 7, 0, edx, 1, sgx_keys , Intel SGX attestation services
247 … 7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions
248 …7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single prec…
249 7, 0, edx, 4, fsrm , Fast short REP MOV
250 7, 0, edx, 5, uintr , CPU supports user interrupts
251 7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions
252 7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR available
253 7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode support
254 … 7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts
255 …7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit, suppo…
256 7, 0, edx, 14, serialize , SERIALIZE instruction
257 … 7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part'
258 … 7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking
259 7, 0, edx, 18, pconfig , PCONFIG instruction
260 7, 0, edx, 19, arch_lbr , Intel architectural LBRs
261 7, 0, edx, 20, ibt , CET indirect branch tracking
262 7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support
263 7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions
264 … 7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support
265 … 7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support
266 …7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect …
267 … 7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors
268 … 7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR
269 7, 0, edx, 29, arch_capabilities , Intel IA32_ARCH_CAPABILITIES MSR
270 7, 0, edx, 30, core_capabilities , IA32_CORE_CAPABILITIES MSR
271 7, 0, edx, 31, spec_ctrl_ssbd , Speculative store bypass disable
289 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-INT8 instructions
290 7, 1, edx, 5, avx_ne_convert , AVX-NE-CONVERT instructions
291 …7, 1, edx, 8, amx_complex , AMX-COMPLEX instructions (starting from G…
292 7, 1, edx, 14, prefetchit_0_1 , PREFETCHIT0/1 instructions
293 … 7, 1, edx, 18, cet_sss , CET supervisor shadow stacks safe to use
294 … 7, 2, edx, 0, intel_psfd , Intel predictive store forward disable
295 … 7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
296 … 7, 2, edx, 2, rrsba_ctrl , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
297 7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
298 7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
299 7, 2, edx, 5, mcdt_no , MCDT mitigation not needed
300 7, 2, edx, 6, uclock_disable , UC-lock disable is supported
323 0xa, 0, edx, 4:0, pmu_n_fcounters , Number of fixed PMU counters
324 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth of PMU fixed counters
325 0xa, 0, edx, 15, anythread_depr , AnyThread deprecation
334 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
354 …0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-…
378 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring supported
383 … 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring supported
384 …0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring suppo…
385 …0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring suppo…
398 …0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max COS (Class of Service) s…
402 0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service supported
416 …0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mod…
417 …0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (l…
442 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC section size, bits[32:51]
488 …0x17, 0, edx, 31:0, soc_stepping_id , Soc project stepping ID, assigned by v…
492 …0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_…
505 0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type)
506 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)
507 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative structure
508 …0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max num of addressible IDs for logical…
534 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A supported PCONFIG target ID
580 0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
593 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7
623 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11
631 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7
670 0x80000001, 0, edx, 0, e_fpu , Floating-Point Unit on-chip (x87)
671 0x80000001, 0, edx, 1, e_vme , Virtual-8086 Mode Extensions
672 0x80000001, 0, edx, 2, e_de , Debugging Extensions
673 0x80000001, 0, edx, 3, e_pse , Page Size Extension
674 0x80000001, 0, edx, 4, e_tsc , Time Stamp Counter
675 0x80000001, 0, edx, 5, e_msr , Model-Specific Registers (RDMSR a…
676 0x80000001, 0, edx, 6, pae , Physical Address Extensions
677 0x80000001, 0, edx, 7, mce , Machine Check Exception
678 0x80000001, 0, edx, 8, cx8 , CMPXCHG8B instruction
679 0x80000001, 0, edx, 9, apic , APIC on-chip
680 0x80000001, 0, edx, 11, syscall , SYSCALL and SYSRET instructions
681 0x80000001, 0, edx, 12, mtrr , Memory Type Range Registers
682 0x80000001, 0, edx, 13, pge , Page Global Extensions
683 0x80000001, 0, edx, 14, mca , Machine Check Architecture
684 0x80000001, 0, edx, 15, cmov , Conditional Move Instruction
685 0x80000001, 0, edx, 16, pat , Page Attribute Table
686 0x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit)
687 0x80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing b…
688 0x80000001, 0, edx, 20, nx , No-execute page protection
689 0x80000001, 0, edx, 22, mmxext , AMD MMX extensions
690 0x80000001, 0, edx, 24, e_fxsr , FXSAVE and FXRSTOR instructions
691 0x80000001, 0, edx, 25, fxsr_opt , FXSAVE and FXRSTOR optimizations
692 0x80000001, 0, edx, 26, pdpe1gb , 1-GB large page support
693 0x80000001, 0, edx, 27, rdtscp , RDTSCP instruction
694 0x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support)
695 0x80000001, 0, edx, 30, 3dnowext , AMD 3DNow extensions
696 0x80000001, 0, edx, 31, 3dnow , 3DNow instructions
704 0x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand ID string, bytes 12 - 15
712 0x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand ID string bytes, 28 - 31
720 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47
737 0x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icache line size, in bytes
738 0x80000005, 0, edx, 15:8, l1_icache_nlines , L1 icache lines per tag
739 0x80000005, 0, edx, 23:16, l1_icache_assoc , L1 icache associativity
740 0x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icache size, in KB
757 0x80000006, 0, edx, 7:0, l3_line_size , L3 cache line size, in bytes
758 0x80000006, 0, edx, 11:8, l3_nlines , L3 cache number of lines per tag
759 0x80000006, 0, edx, 15:12, l3_assoc , L3 cache associativity
760 0x80000006, 0, edx, 31:18, l3_size_range , L3 cache size range
770 0x80000007, 0, edx, 0, digital_temp , Digital temprature sensor
771 0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW! frequency scaling
772 0x80000007, 0, edx, 2, powernow_volt_id , PowerNOW! voltage scaling
773 0x80000007, 0, edx, 3, thermal_trip , THERMTRIP (Thermal Trip)
774 0x80000007, 0, edx, 4, hw_thermal_control , Hardware thermal control
775 0x80000007, 0, edx, 5, sw_thermal_control , Software thermal control
776 0x80000007, 0, edx, 6, 100mhz_steps , 100 MHz multiplier control
777 0x80000007, 0, edx, 7, hw_pstate , Hardware P-state control
778 0x80000007, 0, edx, 8, constant_tsc , TSC ticks at constant rate across…
779 0x80000007, 0, edx, 9, cpb , Core performance boost
780 0x80000007, 0, edx, 10, eff_freq_ro , Read-only effective frequency int…
781 0x80000007, 0, edx, 11, proc_feedback , Processor feedback interface (dep…
782 0x80000007, 0, edx, 12, acc_power , Processor power reporting interfa…
783 0x80000007, 0, edx, 13, connected_standby , CPU Connected Standby support
784 0x80000007, 0, edx, 14, rapl , Runtime Average Power Limit inter…
822 0x80000008, 0, edx, 15:0, invlpgb_max_pages , INVLPGB maximum page count
823 0x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU max register ID (ECX input)
830 0x8000000a, 0, edx, 0, npt , Nested paging
831 0x8000000a, 0, edx, 1, lbrv , LBR virtualization
832 0x8000000a, 0, edx, 2, svm_lock , SVM lock
833 0x8000000a, 0, edx, 3, nrip_save , NRIP save support on #VMEXIT
834 0x8000000a, 0, edx, 4, tsc_scale , MSR based TSC rate control
835 0x8000000a, 0, edx, 5, vmcb_clean , VMCB clean bits support
836 0x8000000a, 0, edx, 6, flushbyasid , Flush by ASID + Extended VMCB TLB…
837 0x8000000a, 0, edx, 7, decodeassists , Decode Assists support
838 0x8000000a, 0, edx, 10, pausefilter , Pause intercept filter
839 0x8000000a, 0, edx, 12, pfthreshold , Pause filter threshold
840 0x8000000a, 0, edx, 13, avic , Advanced virtual interrupt contro…
841 0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual VMSAVE/VMLOAD (nested vir…
842 0x8000000a, 0, edx, 16, vgif , Virtualize the Global Interrupt F…
843 0x8000000a, 0, edx, 17, gmet , Guest mode execution trap
844 0x8000000a, 0, edx, 18, x2avic , Virtual x2APIC
845 0x8000000a, 0, edx, 19, sss_check , Supervisor Shadow Stack restricti…
846 0x8000000a, 0, edx, 20, v_spec_ctrl , Virtual SPEC_CTRL
847 0x8000000a, 0, edx, 21, ro_gpt , Read-Only guest page table support
848 0x8000000a, 0, edx, 23, h_mce_override , Host MCE override
849 0x8000000a, 0, edx, 24, tlbsync_int , TLBSYNC intercept + INVLPGB/TLBSY…
850 0x8000000a, 0, edx, 25, vnmi , NMI virtualization
851 0x8000000a, 0, edx, 26, ibs_virt , IBS Virtualization
852 0x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended LVT offset fault change
853 0x8000000a, 0, edx, 28, svme_addr_chk , Guest SVME addr check
916 0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is available in Hardware
917 0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL instruction (EventId=1) is…
918 0x8000001c, 0, edx, 2, hw_lwp_ire , Instructions Retired Event (Event…
919 0x8000001c, 0, edx, 3, hw_lwp_bre , Branch Retired Event (EventId=3) …
920 0x8000001c, 0, edx, 4, hw_lwp_dme , DCache Miss Event (EventId=4) is …
921 0x8000001c, 0, edx, 5, hw_lwp_cnh , CPU Clocks Not Halted event (Even…
922 0x8000001c, 0, edx, 6, hw_lwp_rnh , CPU Reference clocks Not Halted e…
923 0x8000001c, 0, edx, 29, hw_lwp_cont , LWP sampling in continuous mode i…
924 0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performance Time Stamp Counter in…
925 0x8000001c, 0, edx, 31, hw_lwp_int , Interrupt on threshold overflow i…
939 0x8000001d, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Re…
940 0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level…
982 0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum ASID for SEV-enabled SEV-…
992 0x80000020, 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (…
994 0x80000020, 2, edx, 31:0, smba_cos_max , SMBA max Class of Service number …
1053 0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU