Lines Matching +full:7 +full:- +full:1
1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v2.4
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
20 # Leaf 1H
24 0x1, 0, eax, 7:4, base_model , Base CPU model ID
29 0x1, 0, ebx, 7:0, brand_id , Brand index
34 0x1, 0, ecx, 1, pclmulqdq , PCLMULQDQ instruction support
35 0x1, 0, ecx, 2, dtes64 , 64-bit DS save area
40 0x1, 0, ecx, 7, est , Enhanced Intel SpeedStep
49 0x1, 0, ecx, 17, pcid , Process-context identifiers
51 0x1, 0, ecx, 19, sse4_1 , SSE4.1
56 0x1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation
61 0x1, 0, ecx, 29, f16c , Half-precision floating-point conversion support
63 0x1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system
64 0x1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)
65 0x1, 0, edx, 1, vme , Virtual-8086 Mode Extensions
69 0x1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR support)
71 0x1, 0, edx, 7, mce , Machine Check Exception
73 0x1, 0, edx, 9, apic , APIC on-chip
80 0x1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
90 0x1, 0, edx, 28, ht , Hyper-threading
92 0x1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now reserved
96 # Intel cache and TLB information one-byte descriptors
98 0x2, 0, eax, 7:0, iteration_count , Number of times this leaf must be queried
99 0x2, 0, eax, 15:8, desc1 , Descriptor #1
102 0x2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
103 0x2, 0, ebx, 7:0, desc4 , Descriptor #4
106 0x2, 0, ebx, 30:24, desc7 , Descriptor #7
107 0x2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
108 0x2, 0, ecx, 7:0, desc8 , Descriptor #8
112 0x2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set
113 0x2, 0, edx, 7:0, desc12 , Descriptor #12
117 0x2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
123 0x4, 31:0, eax, 7:5, cache_level , Cache level (1-based)
124 0x4, 31:0, eax, 8, cache_self_init , Self-initializing cache level
125 0x4, 31:0, eax, 9, fully_associative , Fully-associative cache
128 0x4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
129 0x4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
130 0x4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
131 0x4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
132 0x4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
133 0x4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
134 0x4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function)
139 0x5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes
140 0x5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes
142 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is supported
143 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using MWAIT
144 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using MWAIT
145 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using MWAIT
146 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using MWAIT
147 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using MWAIT
148 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using MWAIT
149 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using MWAIT
150 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using MWAIT
156 0x6, 0, eax, 1, turbo_boost , Intel Turbo Boost
157 0x6, 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-state)
161 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers are supported
181 0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
185 # Leaf 7H
190 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR supported
192 0x7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1
196 0x7, 0, ebx, 7, smep , Supervisor Mode Execution Protection
201 0x7, 0, ebx, 12, cqm , Intel RDT-CMT / AMD Platform-QoS cache monitoring
204 0x7, 0, ebx, 15, rdt_a , Intel RDT / AMD Platform-QoS Enforcement
205 0x7, 0, ebx, 16, avx512f , AVX-512 foundation instructions
206 0x7, 0, ebx, 17, avx512dq , AVX-512 double/quadword instructions
210 0x7, 0, ebx, 21, avx512ifma , AVX-512 integer fused multiply add
214 0x7, 0, ebx, 26, avx512pf , AVX-512 prefetch instructions
215 0x7, 0, ebx, 27, avx512er , AVX-512 exponent/reciprocal instructions
216 0x7, 0, ebx, 28, avx512cd , AVX-512 conflict detection instructions
218 0x7, 0, ebx, 30, avx512bw , AVX-512 byte/word instructions
219 0x7, 0, ebx, 31, avx512vl , AVX-512 VL (128/256 vector length) extensions
221 0x7, 0, ecx, 1, avx512vbmi , AVX-512 Vector byte manipulation instructions
223 0x7, 0, ecx, 3, pku , Protection keys for user-space
226 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 vector byte manipulation instructions group 2
227 0x7, 0, ecx, 7, cet_ss , CET shadow stack features
230 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support
232 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 bitwise algorithms
234 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512: POPCNT for vectors of DWORD/QWORD
235 0x7, 0, ecx, 16, la57 , 57-bit linear addresses (five-level paging)
236 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode
239 0x7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection
245 0x7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages
246 0x7, 0, edx, 1, sgx_keys , Intel SGX attestation services
247 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions
248 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision
262 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support
263 0x7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions
264 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support
265 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support
272 0x7, 1, eax, 4, avx_vnni , AVX-VNNI instructions
273 0x7, 1, eax, 5, avx512_bf16 , AVX-512 bfloat16 instructions
274 0x7, 1, eax, 6, lass , Linear address space separation
275 0x7, 1, eax, 7, cmpccxadd , CMPccXADD instructions
276 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23 is supported
277 0x7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB
278 0x7, 1, eax, 11, fsrs , Fast short REP STOSB
279 0x7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB
280 0x7, 1, eax, 17, fred , FRED: Flexible return and event delivery transitions
281 0x7, 1, eax, 18, lkgs , LKGS: Load 'kernel' (userspace) GS
282 0x7, 1, eax, 19, wrmsrns , WRMSRNS instruction (WRMSR-non-serializing)
283 0x7, 1, eax, 20, nmi_src , NMI-source reporting with FRED event data
284 0x7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations
285 0x7, 1, eax, 22, hreset , History reset support
286 0x7, 1, eax, 23, avx_ifma , Integer fused multiply add
287 0x7, 1, eax, 26, lam , Linear address masking
288 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions
289 0x7, 1, ebx, 0, intel_ppin , Protected processor inventory number (PPIN{,_CTL} MSRs)
290 0x7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-INT8 instructions
291 0x7, 1, edx, 5, avx_ne_convert , AVX-NE-CONVERT instructions
292 0x7, 1, edx, 8, amx_complex , AMX-COMPLEX instructions (starting from Granite Rapids)
293 0x7, 1, edx, 14, prefetchit_0_1 , PREFETCHIT0/1 instructions
294 0x7, 1, edx, 18, cet_sss , CET supervisor shadow stacks safe to use
296 0x7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
301 0x7, 2, edx, 6, uclock_disable , UC-lock disable is supported
311 0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID
316 0xa, 0, ebx, 1, no_insn_retired_evt , Instruction retired event not available
318 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-reference event not available
319 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses event not available
322 0xa, 0, ebx, 7, no_td_slots_evt , Topdown slots event not available
323 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bitmap
331 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)
332 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain
333 0xb, 1:0, ecx, 7:0, domain_nr , This domain level (subleaf ID)
334 0xb, 1:0, ecx, 15:8, domain_type , This domain type
335 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
341 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (bit 1) supported
343 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)
345 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)
346 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)
347 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)
355 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling)
356 0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction
357 0xd, 1, eax, 1, xsavec , XSAVEC instruction
358 0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1
359 0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MSR)
360 0xd, 1, eax, 4, xfd , Extended feature disable support
361 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE area size, all XCR0 and XMMS features enabled
362 0xd, 1, ecx, 8, xss_pt , PT state, supported
363 0xd, 1, ecx, 10, xss_pasid , PASID state, supported
364 0xd, 1, ecx, 11, xss_cet_u , CET user state, supported
365 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state, supported
366 0xd, 1, ecx, 13, xss_hdc , HDC state, supported
367 0xd, 1, ecx, 14, xss_uintr , UINTR state, supported
368 0xd, 1, ecx, 15, xss_lbr , LBR state, supported
369 0xd, 1, ecx, 16, xss_hwp , HWP state, supported
370 0xd, 63:2, eax, 31:0, xsave_sz , Size of save area for subleaf-N feature, in bytes
371 0xd, 63:2, ebx, 31:0, xsave_offset , Offset of save area for subleaf-N feature, in bytes
373 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N feature XSAVE area is 64-byte aligned
378 0xf, 0, ebx, 31:0, core_rmid_max , RMID max, within this core, all types (0-based)
379 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring supported
380 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-based)
381 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit
382 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR conversion factor to bytes
383 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID
384 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring supported
385 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring supported
386 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring supported
391 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology supported
394 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation
395 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT bitmap of allocation units
396 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT COS updates should be infrequent
397 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT CDP (Code and Data Prioritization)
398 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value supported
399 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max COS (Class of Service) supported
400 0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one notation
401 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls are supported
409 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions supported
412 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 supported
416 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: reporting #CP exceptions inside enclave supported
417 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mode (log2)
418 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (log2)
419 0x12, 1, eax, 0, secs_attr_init , ATTRIBUTES.INIT supported (enclave initialized by EINIT)
420 0x12, 1, eax, 1, secs_attr_debug , ATTRIBUTES.DEBUG supported (enclave permits debugger read/write)
421 0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUTES.MODE64BIT supported (enclave runs in 64-bit mode)
422 0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUTES.PROVISIONKEY supported (provisioning key available)
423 0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBUTES.EINITTOKEN_KEY supported (EINIT token key available)
424 0x12, 1, eax, 6, secs_attr_cet , ATTRIBUTES.CET supported (enable CET attributes)
425 0x12, 1, eax, 7, secs_attr_kss , ATTRIBUTES.KSS supported (Key Separation and Sharing enabled)
426 0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUTES.AEXNOTIFY supported (enclave threads may get AEX notifications
427 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 (bit 0) supported
428 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE (bit 1) supported
429 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX (bit 2) supported
430 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)
431 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)
432 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)
433 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)
434 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)
435 0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU registers)
436 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)
437 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA)
450 0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mode
451 0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT MSRs preservation
452 0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets suppression
456 0x14, 0, ebx, 7, event_trace , Event Trace packet generation through IA32_RTIT_CTL.EventEn
459 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries
460 0x14, 0, ecx, 2, single_range_output , Single-range output scheme supported
463 0x14, 1, eax, 2:0, num_address_ranges , Filtering number of configurable Address Ranges
464 0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap of supported MTC period encodings
465 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap of supported Cycle Threshold encodings
466 0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap of supported Configurable PSB frequency encodings
490 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)
491 0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_nr * (4 -> 7)
492 0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_nr * (8 -> 11)
493 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_nr * (12 -> 15)
499 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-page entries supported
500 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-page entries supported
501 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-page entries supported
502 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-page entries supported
507 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)
508 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative structure
509 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max number of addressable IDs for logical CPUs sharing this TLB - 1
514 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction supported
515 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction supported
516 0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction supported
521 0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization (KeySource encoding 1) supported
523 # Leaf 1AH
529 # Leaf 1BH
537 # Leaf 1CH
541 0x1c, 0, eax, 1, lbr_depth_16 , Max stack depth (number of LBR entries) = 16
547 0x1c, 0, eax, 7, lbr_depth_64 , Max stack depth (number of LBR entries) = 64
548 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > C1
550 0x1c, 0, ebx, 0, lbr_cpl , CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported
551 0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported
552 0x1c, 0, ebx, 2, lbr_call_stack , Call-stack mode (IA32_LBR_CTL[3] = 1) supported
554 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs (CPU cycles since last LBR entry) supported
556 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters
558 # Leaf 1DH
562 0x1d, 1, eax, 15:0, amx_palette_size , AMX palette total tiles size, in bytes
563 0x1d, 1, eax, 31:16, amx_tile_size , AMX single tile's size, in bytes
564 0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile single row's size, in bytes
565 0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX palette number of tiles
566 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile max number of rows
568 # Leaf 1EH
569 # Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration
571 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit maximum height, K (rows or columns)
574 # Leaf 1FH
579 0x1f, 5:0, ecx, 7:0, domain_level , This domain level (subleaf ID)
586 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x20 max subleaf + 1
592 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3
593 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11
594 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7
599 0x23, 0, eax, 1, subleaf_1_counters , Subleaf 1, PMU counters bitmaps, is valid
602 0x23, 0, ebx, 1, zbit , IA32_PERFEVTSELx MSRs Z-bit is supported
603 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-purpose PMU counters bitmap
604 0x23, 1, ebx, 31:0, pmu_f_counters_bitmap , Fixed PMU counters bitmap
606 0x23, 3, eax, 1, insn_retired_evt , Instructions retired event supported
608 0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event supported
609 0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event supported
612 0x23, 3, eax, 7, td_slots_evt , Topdown slots event supported
622 0x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor ID string bytes 0 - 3
623 0x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor ID string bytes 4 - 7
624 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11
630 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID string bytes 0 - 3
631 0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID string bytes 8 - 11
632 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7
638 0x80000001, 0, eax, 7:4, e_base_model , Base processor model
645 0x80000001, 0, ecx, 0, lahf_lm , LAHF and SAHF in 64-bit mode
646 0x80000001, 0, ecx, 1, cmp_legacy , Multi-processing legacy mode (No HT)
652 0x80000001, 0, ecx, 7, misalignsse , Misaligned SSE mode
660 0x80000001, 0, ecx, 16, fma4 , 4-operand FMA instruction
668 0x80000001, 0, ecx, 27, ptsc , Performance time-stamp counter
672 0x80000001, 0, edx, 0, e_fpu , Floating-Point Unit on-chip (x87)
673 0x80000001, 0, edx, 1, e_vme , Virtual-8086 Mode Extensions
677 0x80000001, 0, edx, 5, e_msr , Model-Specific Registers (RDMSR and WRMSR support)
679 0x80000001, 0, edx, 7, mce , Machine Check Exception
681 0x80000001, 0, edx, 9, apic , APIC on-chip
688 0x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit)
689 0x80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing bit
690 0x80000001, 0, edx, 20, nx , No-execute page protection
695 0x80000001, 0, edx, 26, pdpe1gb , 1-GB large page support
697 0x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support)
702 # CPU brand ID string, bytes 0 - 15
704 0x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU brand ID string, bytes 0 - 3
705 0x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU brand ID string, bytes 4 - 7
706 0x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU brand ID string, bytes 8 - 11
707 0x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand ID string, bytes 12 - 15
710 # CPU brand ID string, bytes 16 - 31
712 0x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU brand ID string bytes, 16 - 19
713 0x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU brand ID string bytes, 20 - 23
714 0x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU brand ID string bytes, 24 - 27
715 0x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand ID string bytes, 28 - 31
718 # CPU brand ID string, bytes 32 - 47
720 0x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU brand ID string, bytes 32 - 35
721 0x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU brand ID string, bytes 36 - 39
722 0x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU brand ID string, bytes 40 - 43
723 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47
728 0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB #entries, 2M and 4M pages
732 0x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB #entries, 4K pages
736 0x80000005, 0, ecx, 7:0, l1_dcache_line_size , L1 dcache line size, in bytes
740 0x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icache line size, in bytes
756 0x80000006, 0, ecx, 7:0, l2_line_size , L2 cache line size, in bytes
760 0x80000006, 0, edx, 7:0, l3_line_size , L3 cache line size, in bytes
769 0x80000007, 0, ebx, 1, succor , Software containment of uncorrectable errors
774 0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW! frequency scaling
780 0x80000007, 0, edx, 7, hw_pstate , Hardware P-state control
783 0x80000007, 0, edx, 10, eff_freq_ro , Read-only effective frequency interface
792 0x80000008, 0, eax, 7:0, phys_addr_bits , Max physical address bits
794 0x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested-paging guest physical address bits
796 0x80000008, 0, ebx, 1, irperf , Instruction retired counter MSR
807 0x80000008, 0, ebx, 16, ibrs_always_on , IBRS always-on preferred
808 0x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP always-on preferred
811 0x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMSLE] bit (Long-Mode Segment Limit Enable) unsupported
822 0x80000008, 0, ecx, 7:0, cpu_nthreads , Number of physical threads - 1
824 0x80000008, 0, ecx, 17:16, perf_tsc_len , Performance time-stamp counter size
831 0x8000000a, 0, eax, 7:0, svm_version , SVM revision number
834 0x8000000a, 0, edx, 1, lbrv , LBR virtualization
840 0x8000000a, 0, edx, 7, decodeassists , Decode Assists support
850 0x8000000a, 0, edx, 21, ro_gpt , Read-Only guest page table support
859 # AMD TLB 1G-pages enumeration
861 0x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB #entries, 1G pages
862 0x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB associativity, 1G pages
863 0x80000019, 0, eax, 27:16, l1_dtlb_1g_nentries , L1 dTLB #entries, 1G pages
864 0x80000019, 0, eax, 31:28, l1_dtlb_1g_assoc , L1 dTLB associativity, 1G pages
865 0x80000019, 0, ebx, 11:0, l2_itlb_1g_nentries , L2 iTLB #entries, 1G pages
866 0x80000019, 0, ebx, 15:12, l2_itlb_1g_assoc , L2 iTLB associativity, 1G pages
867 0x80000019, 0, ebx, 27:16, l2_dtlb_1g_nentries , L2 dTLB #entries, 1G pages
868 0x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB associativity, 1G pages
873 0x8000001a, 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide
874 0x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH*
875 0x8000001a, 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide
878 # AMD IBS (Instruction-Based Sampling) enumeration
881 0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch sampling supported
886 0x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bits
887 0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invalid RIP indication supported
888 0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indication supported
891 0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering supported (Zen4+)
897 0x8000001c, 0, eax, 1, os_lpwval , LWPVAL instruction is supported by OS
906 0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Control Block size, in quadwords
917 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events can be filtered by cache level
918 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events can be filtered by latency
920 0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL instruction is available in hardware
934 0x8000001d, 31:0, eax, 7:5, cache_level , Cache level (1-based)
935 0x8000001d, 31:0, eax, 8, cache_self_init , Self-initializing cache level
936 0x8000001d, 31:0, eax, 9, fully_associative , Fully-associative cache
938 0x8000001d, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
939 0x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
940 0x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
941 0x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
942 0x8000001d, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
943 0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
949 0x8000001e, 0, ebx, 7:0, core_id , Unique per-socket logical core unit ID
950 0x8000001e, 0, ebx, 15:8, core_nthreas , #Threads per core (zero-based)
951 0x8000001e, 0, ecx, 7:0, node_id , Node (die) ID of invoking logical CPU
958 0x8000001f, 0, eax, 1, sev , Secure Encrypted Virtualization supported
964 0x8000001f, 0, eax, 7, vmpl_sss , VMPL supervisor shadow stack supported
968 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervisor
971 0x8000001f, 0, eax, 14, debug_swap , SEV-ES: full debug state swap is supported
972 0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by the host is supported
976 0x8000001f, 0, eax, 19, virt_ibs , IBS state virtualization is supported for SEV-ES guests
985 0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Minimum ASID for SEV-enabled SEV-ES-disabled guest
990 0x80000020, 0, ebx, 1, mba , Memory Bandwidth Allocation support
996 0x80000020, 1, eax, 31:0, mba_limit_len , MBA enforcement limit size
997 0x80000020, 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (zero-based)
999 0x80000020, 2, edx, 31:0, smba_cos_max , SMBA max Class of Service number (zero-based)
1000 0x80000020, 3, ebx, 7:0, bmec_num_events , BMEC number of bandwidth events available
1002 0x80000020, 3, ecx, 1, bmec_remote_reads , Remote NUMA reads can be tracked
1003 0x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NUMA non-temporal writes can be tracked
1004 0x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote NUMA non-temporal writes can be tracked
1005 0x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NUMA slow-memory reads can be tracked
1006 0x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote NUMA slow-memory reads can be tracked
1013 0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
1017 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore
1026 0x80000021, 0, eax, 22, wl_feedback , Workload-based heuristic feedback to OS
1031 0x80000021, 0, eax, 30, srso_uk_no , CPU is not vulnerable to SRSO at user-kernel boundary
1033 0x80000021, 0, ebx, 15:0, microcode_patch_size , Size of microcode patch, in 16-byte units
1040 0x80000022, 0, eax, 1, lbr_v2 , Last Branch Record v2 extensions (LBR Stack)
1049 # AMD Secure Multi-key Encryption enumeration
1051 0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode is supported
1052 0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK mode: total number of available encryption keys
1065 0x80000026, 3:0, ecx, 7:0, domain_level , This domain level (subleaf ID)
1073 0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmeta Vendor ID string bytes 0 - 3
1074 0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmeta Vendor ID string bytes 8 - 11
1075 0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmeta Vendor ID string bytes 4 - 7
1081 0x80860001, 0, eax, 7:4, base_model , Base CPU model ID
1084 0x80860001, 0, ebx, 7:0, cpu_rev_mask_minor , CPU revision ID, mask minor
1090 0x80860001, 0, edx, 1, longrun , LongRun power management capabilities
1097 0x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revision ID, mask component 2
1098 0x80860002, 0, ebx, 15:8, cms_rev_mask_1 , CMS revision ID, mask component 1
1104 # Transmeta CPU information string, bytes 0 - 15
1106 0x80860003, 0, eax, 31:0, cpu_info_0 , CPU info string bytes 0 - 3
1107 0x80860003, 0, ebx, 31:0, cpu_info_1 , CPU info string bytes 4 - 7
1108 0x80860003, 0, ecx, 31:0, cpu_info_2 , CPU info string bytes 8 - 11
1109 0x80860003, 0, edx, 31:0, cpu_info_3 , CPU info string bytes 12 - 15
1112 # Transmeta CPU information string, bytes 16 - 31
1114 0x80860004, 0, eax, 31:0, cpu_info_4 , CPU info string bytes 16 - 19
1115 0x80860004, 0, ebx, 31:0, cpu_info_5 , CPU info string bytes 20 - 23
1116 0x80860004, 0, ecx, 31:0, cpu_info_6 , CPU info string bytes 24 - 27
1117 0x80860004, 0, edx, 31:0, cpu_info_7 , CPU info string bytes 28 - 31
1120 # Transmeta CPU information string, bytes 32 - 47
1122 0x80860005, 0, eax, 31:0, cpu_info_8 , CPU info string bytes 32 - 35
1123 0x80860005, 0, ebx, 31:0, cpu_info_9 , CPU info string bytes 36 - 39
1124 0x80860005, 0, ecx, 31:0, cpu_info_10 , CPU info string bytes 40 - 43
1125 0x80860005, 0, edx, 31:0, cpu_info_11 , CPU info string bytes 44 - 47
1128 # Transmeta CPU information string, bytes 48 - 63
1130 0x80860006, 0, eax, 31:0, cpu_info_12 , CPU info string bytes 48 - 51
1131 0x80860006, 0, ebx, 31:0, cpu_info_13 , CPU info string bytes 52 - 55
1132 0x80860006, 0, ecx, 31:0, cpu_info_14 , CPU info string bytes 56 - 59
1133 0x80860006, 0, edx, 31:0, cpu_info_15 , CPU info string bytes 60 - 63
1140 0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current CPU performance percentage, 0 - 100
1152 0xc0000001, 0, edx, 1, ccs_sm2_en , CCS SM2 enabled
1158 0xc0000001, 0, edx, 7, ace_en , ACE enabled