Lines Matching +full:use +full:- +full:rtm

1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* x86-64 specific MSRs */
23 #define _EFER_LMA		10 /* Long mode active (read-only) */
130 #define ARCH_CAP_RSBA			BIT(2)	/* RET may use alternative branch predictors */
179 						 * Indicates RET may use predictors
194 						 * Not susceptible to Post-Barrier
233 #define TSX_CTRL_RTM_DISABLE		BIT(0)	/* Disable RTM feature */
294 #define LBR_INFO_BR_CNTR_MASK		GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0)
295 #define LBR_INFO_BR_CNTR_FULL_MASK	GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0)
416 #define DEBUGCTLMSR_BTF			(1UL <<  1) /* single-step on branches */
436 /* C-state Residency Counters */
516 /* Control-flow Enforcement Technology MSRs */
529 #define MSR_IA32_PL0_SSP		0x000006a4 /* ring-0 shadow stack pointer */
530 #define MSR_IA32_PL1_SSP		0x000006a5 /* ring-1 shadow stack pointer */
531 #define MSR_IA32_PL2_SSP		0x000006a6 /* ring-2 shadow stack pointer */
532 #define MSR_IA32_PL3_SSP		0x000006a7 /* ring-3 shadow stack pointer */
604 /* Auto-reload via MSR instead of DS area */
658 #define MSR_AMD64_IBSFETCH_REG_MASK	((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
667 #define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
737 /* Masks for use with MSR_AMD_CPPC_CAP1 */
743 /* Masks for use with MSR_AMD_CPPC_REQ */
871 /* Centaur-Hauls/IDT defined MSRs. */
1034 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
1066 /* MISC_FEATURES_ENABLES non-architectural features */
1185 /* Intel Core-based CPU performance counters */
1230 /* - Intel: */
1241 /* - AMD: */
1248 /* AMD-V MSRs */