Lines Matching +full:l2 +full:- +full:data +full:- +full:latency
1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include "msr-index.h"
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
39 ic_miss:1, /* 51: i-cache miss */
41 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
43 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
44 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
46 fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
51 reserved:2; /* 62-63: reserved */
59 __u64 opmaxcnt:16, /* 0-15: periodic op max. count */
64 opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
65 reserved0:5, /* 27-31: reserved */
66 opcurcnt:27, /* 32-58: periodic op counter current count */
67 reserved1:5; /* 59-63: reserved */
71 /* MSR 0xc0011035: IBS Op Data 1 */
75 __u64 comp_to_ret_ctr:16, /* 0-15: op completion to retire count */
76 tag_to_ret_ctr:16, /* 15-31: op tag to retire count */
77 reserved1:2, /* 32-33: reserved */
85 reserved2:23; /* 41-63: reserved */
89 /* MSR 0xc0011036: IBS Op Data 2 */
93 __u64 data_src_lo:3, /* 0-2: data source low */
97 data_src_hi:2, /* 6-7: data source high */
98 reserved1:56; /* 8-63: reserved */
102 /* MSR 0xc0011037: IBS Op Data 3 */
108 dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */
109 dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */
110 dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */
111 dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */
112 dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */
113 dc_miss:1, /* 7: data cache miss */
115 reserved:4, /* 9-12: reserved */
120 dc_lin_addr_valid:1, /* 17: data cache linear address valid */
121 dc_phy_addr_valid:1, /* 18: data cache physical address valid */
122 dc_l2_tlb_hit_1g:1, /* 19: data cache L2 hit in 1GB page */
123 l2_miss:1, /* 20: L2 cache miss */
125 op_mem_width:4, /* 22-25: load/store size in bytes */
126 op_dc_miss_open_mem_reqs:6, /* 26-31: outstanding mem reqs on DC fill */
127 dc_miss_lat:16, /* 32-47: data cache miss latency */
128 tlb_refill_lat:16; /* 48-63: L1 TLB refill latency */
136 __u64 itlb_refill_lat:16, /* 0-15: ITLB Refill latency for sampled fetch */
137 reserved:48; /* 16-63: reserved */
148 u32 data[0]; /* data buffer starts here */ member