Lines Matching +full:8 +full:- +full:n +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
34 #define CRm_shift 8
59 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
76 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
97 #define PSTATE_SSBS pstate_field(3, 1)
112 /* Register-based PAN access, for save/restore purposes */
121 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
122 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
123 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
124 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
125 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
126 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
127 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
128 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
129 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
131 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
132 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
133 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
135 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
136 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
137 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
139 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
140 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
141 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
143 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
145 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
146 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
147 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
149 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
150 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
151 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
153 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
154 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
155 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
157 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
161 #define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1)
162 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
170 #include "asm/sysreg-defs.h"
174 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
180 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) argument
181 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) argument
182 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) argument
183 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) argument
184 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
186 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
190 #define OSLSR_EL1_OSLK BIT(1)
192 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
193 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
194 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
197 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
203 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0)) argument
204 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
205 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1)) argument
206 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
207 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2)) argument
208 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
209 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
211 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
212 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
213 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
215 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
216 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
217 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
218 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
219 #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
220 #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
221 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
222 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
223 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
224 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
225 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
226 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
227 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
228 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
229 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
230 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
231 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
232 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
233 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
234 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
235 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
236 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
237 #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
238 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
239 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
240 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
241 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
242 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
243 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
244 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
245 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
246 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
247 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
248 #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
249 #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
250 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
251 #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
252 #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
253 #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
254 #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
255 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
256 #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
257 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
258 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
259 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
260 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
261 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
262 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
263 #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
264 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
265 #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
266 #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
267 #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
268 #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
269 #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
270 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
271 #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
272 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
273 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
274 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
277 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
285 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
286 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
287 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
291 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
292 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
293 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
294 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
297 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
302 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
305 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
309 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
310 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
314 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
316 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
323 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
327 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
332 /* When PAR_EL1.F == 1 */
333 #define SYS_PAR_EL1_FST GENMASK(6, 1)
334 #define SYS_PAR_EL1_PTW BIT(8)
344 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
350 #define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
354 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
375 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
384 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
386 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
387 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
388 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
389 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
390 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) argument
392 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
395 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) argument
397 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
400 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
406 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
416 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
418 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
421 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
424 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
431 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
445 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
451 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
456 * Counter: 11 011 1101 010:n<3> n<2:0>
457 * Type: 11 011 1101 011:n<3> n<2:0>
458 * n: 0-15
460 * Group 1 of activity monitors (auxiliary):
462 * Counter: 11 011 1101 110:n<3> n<2:0>
463 * Type: 11 011 1101 111:n<3> n<2:0>
464 * n: 0-15
467 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) argument
468 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) argument
469 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) argument
470 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) argument
474 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
480 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
486 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
490 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
494 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
496 #define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0)
498 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
501 #define __PMEV_op2(n) ((n) & 0x7) argument
502 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) argument
503 #define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n)) argument
504 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) argument
505 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) argument
506 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) argument
510 #define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1)) argument
512 #define __SPMEV_op2(n) ((n) & 0x7) argument
513 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1)) argument
514 #define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n)) argument
515 #define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n)) argument
516 #define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n)) argument
517 #define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n)) argument
522 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
523 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
524 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
525 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
526 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
527 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
528 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
529 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
532 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
534 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
535 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
539 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
540 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
542 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
545 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
546 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
547 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
560 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
562 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
563 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
565 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
571 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
583 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
593 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
601 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
606 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) argument
613 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
615 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
618 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
621 /* VHE encodings for architectural EL0/1 system registers */
624 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
626 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
627 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
628 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
636 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
638 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
641 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
644 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
647 #define AT_Op0 1
650 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
651 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
652 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
653 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
655 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
657 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
658 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
659 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
660 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
661 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
662 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
666 #define TLBI_Op0 1
671 #define TLBI_CRn_XS 8 /* Extra Slow (the common one) */
674 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
675 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
676 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
677 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
678 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
679 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
680 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
681 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
683 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
684 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
685 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
686 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
687 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
688 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
689 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
690 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
691 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
692 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
693 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
694 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
695 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
696 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
697 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
698 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
699 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
700 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
701 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
702 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
703 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
704 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
705 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
706 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
707 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
708 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
709 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
710 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
711 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
712 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
713 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
714 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
715 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
716 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
717 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
718 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
719 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
720 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
721 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
722 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
723 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
724 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
725 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
726 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
727 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
728 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
729 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
730 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
731 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
732 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
733 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
734 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
735 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
736 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
737 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
738 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
739 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
740 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
741 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
742 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
743 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
744 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
745 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
746 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
747 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
748 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
749 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
750 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
751 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
752 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
753 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
754 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
755 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
756 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
757 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
758 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
759 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
760 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
761 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
762 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
763 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
764 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
765 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
766 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
767 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
768 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
769 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
770 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
771 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
772 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
773 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
774 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
775 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
776 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
777 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
778 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
779 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
780 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
781 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
782 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
783 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
784 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
785 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
786 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
787 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
788 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
789 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
790 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
791 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
792 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
793 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
794 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
795 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
796 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
797 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
798 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
799 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
800 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
801 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
802 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
803 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
804 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
805 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
806 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
807 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
808 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
811 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
812 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
813 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
814 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
816 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
817 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
818 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
819 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
820 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
821 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
847 #define SCTLR_ELx_A (BIT(1))
899 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
960 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
974 #define SYS_RGSR_EL1_SEED_SHIFT 8
979 #define SYS_TFSR_EL1_TF1_SHIFT 1
980 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
981 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
988 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
990 #define ICH_LR_EOI (1ULL << 41)
991 #define ICH_LR_GROUP (1ULL << 60)
992 #define ICH_LR_HW (1ULL << 61)
994 #define ICH_LR_PENDING_BIT (1ULL << 62)
995 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
1003 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
1005 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
1007 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
1009 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
1017 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
1018 #define ICH_VMCR_ENG1_SHIFT 1
1019 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
1102 " .macro mrs_s, rt, sreg\n" \
1104 " .endm\n"
1108 " .macro msr_s, sreg, rt\n" \
1110 " .endm\n"
1113 " .purgem mrs_s\n"
1116 " .purgem msr_s\n"
1120 " mrs_s " v ", " __stringify(r) "\n" \
1125 " msr_s " __stringify(r) ", " v "\n" \
1171 * set mask are set. Other bits are left as-is.