Lines Matching +full:7 +full:- +full:8
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
34 #define CRm_shift 8
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
112 /* Register-based PAN access, for save/restore purposes */
118 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
121 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
122 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
123 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
124 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
125 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
126 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
127 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
128 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
129 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
131 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
132 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
133 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
135 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
136 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
137 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
139 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
140 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
141 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
143 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
145 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
146 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
147 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
149 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
150 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
151 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
153 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
154 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
155 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
157 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
161 #define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1)
162 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
170 #include "asm/sysreg-defs.h"
183 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
194 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
195 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
196 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
201 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
203 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
205 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
207 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
216 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
217 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
218 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
224 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
225 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
226 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
229 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
231 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
232 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
233 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
235 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
236 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
241 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
242 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
243 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
244 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
245 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
246 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
247 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
250 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
259 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
260 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
261 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
262 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
274 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
329 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
334 #define SYS_PAR_EL1_PTW BIT(8)
341 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
344 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
354 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
386 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
387 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
388 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
389 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
390 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
404 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
412 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
418 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
429 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
440 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
458 * n: 0-15
464 * n: 0-15
467 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
468 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
469 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
470 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
498 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
508 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
513 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
529 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
563 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
579 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
589 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
599 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
603 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
635 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
648 #define AT_CRn 7
650 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
651 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
652 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
653 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
657 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
658 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
659 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
660 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
661 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
662 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
671 #define TLBI_CRn_XS 8 /* Extra Slow (the common one) */
674 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
675 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
676 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
677 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
678 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
679 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
680 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
681 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
683 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
684 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
685 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
686 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
687 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
688 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
689 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
690 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
691 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
692 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
693 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
694 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
695 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
696 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
697 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
698 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
699 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
700 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
701 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
702 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
703 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
704 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
705 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
706 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
707 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
708 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
709 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
710 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
711 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
712 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
718 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
722 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
728 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
732 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
736 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
737 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
738 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
739 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
740 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
741 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
742 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
743 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
744 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
745 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
746 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
747 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
748 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
749 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
750 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
751 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
752 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
753 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
754 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
755 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
756 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
757 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
758 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
759 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
760 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
761 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
762 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
763 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
764 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
765 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
766 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
767 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
768 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
769 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
770 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
771 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
772 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
773 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
774 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
775 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
799 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
804 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
805 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
806 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
807 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
808 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
811 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
812 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
813 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
814 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
816 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
817 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
818 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
819 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
820 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
821 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
899 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
960 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
974 #define SYS_RGSR_EL1_SEED_SHIFT 8
988 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1011 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1013 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1171 * set mask are set. Other bits are left as-is.