Lines Matching +full:5 +full:x
26 * [7-5] : Op2
36 #define Op2_shift 5
55 // The space separator is omitted so that __emit_inst(x) can be parsed as
57 #define __emit_inst(x) .inst(x)
59 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" argument
65 #define __INSTR_BSWAP(x) (x) argument
67 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ argument
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
70 (((x) >> 24) & 0x000000ff))
74 #define __emit_inst(x) .long __INSTR_BSWAP(x)
76 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" argument
93 #define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift)) argument
101 #define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN) argument
102 #define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO) argument
103 #define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS) argument
104 #define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT) argument
105 #define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO) argument
107 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) argument
108 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) argument
109 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) argument
110 #define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x)) argument
132 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
133 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
137 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
141 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
147 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
151 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
155 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
162 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
181 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
199 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
200 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
227 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
228 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
229 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
240 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
282 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
286 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
309 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
310 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
311 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
313 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
314 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
315 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
316 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
317 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
318 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
319 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
320 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
321 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
322 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
323 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
324 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
325 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
326 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
327 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
372 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
402 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
410 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
414 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
438 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
449 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
482 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
520 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
545 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
546 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
547 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
548 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
549 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
550 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
551 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
563 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) argument
569 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) argument
576 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
578 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
581 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) argument
587 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
591 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) argument
597 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
622 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
623 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
624 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
625 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
626 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
627 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
628 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
629 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
630 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
631 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
632 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
633 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
634 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
635 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
636 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
637 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
638 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
639 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
640 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
641 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
642 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
660 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
679 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
687 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
691 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
697 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
699 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
700 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
701 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
702 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
705 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
711 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
717 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
721 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
727 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
729 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
730 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
731 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
732 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
735 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
741 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
745 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
750 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
753 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
757 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
764 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
767 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
768 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
770 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
774 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
778 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
783 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
786 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
790 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
797 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
800 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
801 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
803 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
807 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
812 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
817 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
819 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
851 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
1068 #define GCS_CAP_ADDR(x) FIELD_GET(GCS_CAP_ADDR_MASK, x) argument
1073 #define GCS_CAP_TOKEN(x) FIELD_GET(GCS_CAP_TOKEN_MASK, x) argument
1078 #define GCS_CAP(x) ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \ argument