Lines Matching +full:3 +full:- +full:5
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
36 #define Op2_shift 5
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
96 #define PSTATE_UAO pstate_field(0, 3)
97 #define PSTATE_SSBS pstate_field(3, 1)
98 #define PSTATE_DIT pstate_field(3, 2)
99 #define PSTATE_TCO pstate_field(3, 4)
112 /* Register-based PAN access, for save/restore purposes */
113 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
116 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
132 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
133 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
136 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
137 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
139 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
140 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
141 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
143 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
145 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
146 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
147 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
149 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
150 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
151 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
153 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
154 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
155 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
157 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
162 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
170 #include "asm/sysreg-defs.h"
176 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
177 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
178 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
181 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
187 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
189 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
192 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
197 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
198 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
199 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
200 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
215 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
216 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
217 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
222 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
223 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
224 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
227 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
228 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
229 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
235 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
238 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
240 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
257 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
262 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
264 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
270 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
272 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
273 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
274 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
281 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
282 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
283 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
285 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
286 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
287 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
289 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
291 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
292 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
293 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
294 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
296 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
297 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
298 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
299 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
301 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
302 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
304 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
305 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
307 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
309 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
310 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
311 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
313 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
314 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
315 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
316 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
317 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
318 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
319 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
320 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
321 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
322 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
323 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
324 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
325 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
326 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
327 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
329 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
372 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
375 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
376 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
378 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
380 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
381 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
383 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
384 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
386 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
387 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
388 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
389 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
390 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
394 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
395 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
399 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
400 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
401 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
402 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
403 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
404 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
405 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
406 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
407 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
408 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
409 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
410 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
411 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
412 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
414 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
416 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
418 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
420 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
421 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
423 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
424 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
425 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
426 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
427 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
428 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
429 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
430 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
431 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
432 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
433 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
434 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
436 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
437 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
438 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
440 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
443 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
447 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
449 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
450 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
451 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
456 * Counter: 11 011 1101 010:n<3> n<2:0>
457 * Type: 11 011 1101 011:n<3> n<2:0>
458 * n: 0-15
462 * Counter: 11 011 1101 110:n<3> n<2:0>
463 * Type: 11 011 1101 111:n<3> n<2:0>
464 * n: 0-15
467 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
468 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
469 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
470 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
476 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
478 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
480 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
481 #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
482 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
483 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
485 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
486 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
487 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
489 #define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0)
490 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
491 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
502 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
504 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
505 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
506 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
508 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
513 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
514 #define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
515 #define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
516 #define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
517 #define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
519 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
520 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
522 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
523 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
524 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
525 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
526 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
527 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
528 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
529 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
531 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
532 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
533 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
534 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
535 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
537 #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
538 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
539 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
540 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
541 #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
542 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
543 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
544 #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
545 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
546 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
547 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
548 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
549 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
550 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
551 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
553 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
554 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
556 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
557 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
559 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
560 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
561 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
562 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
563 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
567 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
569 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
573 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
575 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
576 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
577 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
578 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
579 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
581 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
585 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
587 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
591 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
595 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
597 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
601 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
602 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
603 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
606 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
607 #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
609 #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
612 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
613 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
614 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
615 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
616 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
617 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
618 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
619 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
622 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
623 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
624 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
625 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
626 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
627 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
628 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
629 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
630 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
631 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
632 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
633 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
634 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
635 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
636 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
637 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
638 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
639 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
640 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
641 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
642 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
644 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
653 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
660 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
674 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
675 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
676 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
677 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
678 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
679 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
680 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
681 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
686 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
687 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
690 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
691 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
693 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
694 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
695 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
696 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
697 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
698 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
699 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
700 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
701 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
702 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
704 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
705 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
710 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
711 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
716 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
717 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
720 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
721 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
723 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
724 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
725 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
726 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
727 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
728 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
729 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
730 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
731 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
732 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
734 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
735 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
740 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
741 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
745 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
750 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
753 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
754 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
755 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
756 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
757 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
758 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
762 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
764 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
767 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
768 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
770 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
774 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
778 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
783 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
786 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
787 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
788 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
789 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
790 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
791 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
795 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
797 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
800 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
801 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
803 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
807 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
812 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
814 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
817 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
818 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
819 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
820 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
821 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
845 #define SCTLR_ELx_SA (BIT(3))
851 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
960 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
988 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
993 #define ICH_LR_STATE (3ULL << 62)
1004 #define ICH_VMCR_FIQ_EN_SHIFT 3
1174 * set mask are set. Other bits are left as-is.