Lines Matching +full:2 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
21 * C5.2, version:ARM DDI 0487A.f)
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
98 #define PSTATE_DIT pstate_field(3, 2)
112 /* Register-based PAN access, for save/restore purposes */
113 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
118 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
121 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
122 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
123 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
124 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
125 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
126 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
127 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
128 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
129 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
131 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
132 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
133 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
135 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
136 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
137 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
139 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
140 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
141 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
143 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
145 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
146 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
147 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
149 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
150 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
151 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
153 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
154 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
155 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
157 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
161 #define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1)
162 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
170 #include "asm/sysreg-defs.h"
176 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
180 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
181 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
182 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
183 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
184 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
186 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
192 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
193 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
194 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
195 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
196 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
197 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
198 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
199 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
200 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
201 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
203 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
204 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
205 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
206 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
207 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
208 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
209 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
211 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
212 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
213 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
215 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
216 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
217 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
218 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
219 #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
220 #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
221 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
222 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
223 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
224 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
225 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
226 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
227 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
228 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
229 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
230 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
231 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
232 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
233 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
234 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
235 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
236 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
237 #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
238 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
239 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
240 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
241 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
242 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
243 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
244 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
245 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
246 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
247 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
248 #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
249 #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
250 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
251 #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
252 #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
253 #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
254 #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
255 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
256 #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
257 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
258 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
259 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
260 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
261 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
262 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
263 #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
264 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
265 #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
266 #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
267 #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
268 #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
269 #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
270 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
271 #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
272 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
273 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
274 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
277 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
279 #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
289 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
291 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
292 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
293 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
294 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
296 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
297 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
298 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
299 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
301 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
302 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
311 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
317 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
324 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
329 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
341 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
344 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
355 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
376 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
380 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
388 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
393 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
398 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
404 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
407 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
412 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
418 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
420 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
421 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
425 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
429 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
432 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
436 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
440 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
444 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
445 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
446 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
447 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
448 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
449 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
456 * Counter: 11 011 1101 010:n<3> n<2:0>
457 * Type: 11 011 1101 011:n<3> n<2:0>
458 * n: 0-15
462 * Counter: 11 011 1101 110:n<3> n<2:0>
463 * Type: 11 011 1101 111:n<3> n<2:0>
464 * n: 0-15
467 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
468 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
469 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
470 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
475 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
481 #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
485 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
486 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
487 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
491 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
493 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
494 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
497 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
503 #define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
508 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
510 #define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1))
513 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
514 #define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
515 #define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
516 #define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
517 #define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
527 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
529 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
531 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
532 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
533 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
534 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
535 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
537 #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
543 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
548 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
549 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
556 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
561 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
566 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
572 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
579 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
584 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
589 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
594 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
599 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
602 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
603 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
614 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
615 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
616 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
619 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
622 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
623 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
624 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
629 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
632 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
635 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
637 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
638 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
639 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
642 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
648 #define AT_CRn 7
652 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
656 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
662 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
663 #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
674 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
675 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
676 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
677 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
678 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
679 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
680 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
681 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
685 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
688 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
689 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
690 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
691 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
692 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
695 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
698 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
702 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
706 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
707 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
708 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
709 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
710 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
711 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
712 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
715 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
718 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
719 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
720 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
721 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
722 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
725 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
728 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
732 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
736 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
737 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
738 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
739 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
740 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
741 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
742 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
744 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
752 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
753 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
761 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
766 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
771 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
772 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
773 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
774 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
775 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
777 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
785 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
786 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
794 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
799 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
804 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
805 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
806 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
807 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
808 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
811 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
812 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
813 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
814 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
816 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
817 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
818 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
819 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
820 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
821 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
846 #define SCTLR_ELx_C (BIT(2))
960 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
988 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1002 #define ICH_VMCR_ACK_CTL_SHIFT 2
1011 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1013 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1171 * set mask are set. Other bits are left as-is.