Lines Matching +full:14 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
112 /* Register-based PAN access, for save/restore purposes */
126 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
127 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
128 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
152 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
153 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
154 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
167 #include "asm/sysreg-defs.h"
184 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
186 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
187 #define OSLSR_EL1_OSLK BIT(1)
193 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
215 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
218 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
243 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
328 #define SYS_PAR_EL1_F BIT(0)
331 #define SYS_PAR_EL1_PTW BIT(8)
332 #define SYS_PAR_EL1_S BIT(9)
333 #define SYS_PAR_EL1_AssuredOnly BIT(12)
334 #define SYS_PAR_EL1_TopLevel BIT(13)
335 #define SYS_PAR_EL1_Overlay BIT(14)
336 #define SYS_PAR_EL1_DirtyBit BIT(15)
338 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
339 #define SYS_PAR_EL1_RES1 BIT(11)
342 #define SYS_PAR_EL1_NS BIT(9)
343 #define SYS_PAR_EL1_F0_IMPDEF BIT(10)
344 #define SYS_PAR_EL1_NSE BIT(11)
372 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
373 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
375 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
413 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
430 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
431 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
455 * n: 0-15
461 * n: 0-15
467 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
475 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
477 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
478 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
479 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
481 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
482 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
483 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
485 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
486 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
488 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
489 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
490 #define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0)
491 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
492 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
496 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
498 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
500 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
599 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
600 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
601 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
602 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
603 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
604 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
605 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
606 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
633 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
634 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
635 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
636 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
637 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
638 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
639 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
671 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
672 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
673 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
674 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
675 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
676 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
677 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
678 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
821 #define SCTLR_ELx_ENTP2 (BIT(60))
822 #define SCTLR_ELx_DSSBS (BIT(44))
823 #define SCTLR_ELx_ATA (BIT(43))
828 #define SCTLR_ELx_ITFSB (BIT(37))
829 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
830 #define SCTLR_ELx_ENIB (BIT(30))
831 #define SCTLR_ELx_LSMAOE (BIT(29))
832 #define SCTLR_ELx_nTLSMD (BIT(28))
833 #define SCTLR_ELx_ENDA (BIT(27))
834 #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT))
835 #define SCTLR_ELx_EIS (BIT(22))
836 #define SCTLR_ELx_IESB (BIT(21))
837 #define SCTLR_ELx_TSCXT (BIT(20))
838 #define SCTLR_ELx_WXN (BIT(19))
839 #define SCTLR_ELx_ENDB (BIT(13))
840 #define SCTLR_ELx_I (BIT(12))
841 #define SCTLR_ELx_EOS (BIT(11))
842 #define SCTLR_ELx_SA (BIT(3))
843 #define SCTLR_ELx_C (BIT(2))
844 #define SCTLR_ELx_A (BIT(1))
845 #define SCTLR_ELx_M (BIT(0))
848 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
849 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
850 (BIT(29)))
852 #define SCTLR_EL2_BT (BIT(36))
941 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
942 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
944 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
945 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
947 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
948 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
951 #define SYS_GCR_EL1_RRND (BIT(16))
957 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
974 /* TFSR{,E0}_EL1 bit definitions */
981 #define SYS_MPIDR_SAFE_VAL (BIT(31))
984 /* ICH_MISR_EL2 bit definitions */
988 /* ICH_LR*_EL2 bit definitions */
989 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1002 /* ICH_HCR_EL2 bit definitions */
1009 #define ICH_HCR_TDIR (1 << 14)
1013 /* ICH_VMCR_EL2 bit definitions */
1033 /* ICH_VTR_EL2 bit definitions */
1173 * set mask are set. Other bits are left as-is.