Lines Matching +full:1 +full:- +full:3
1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/gpr-num.h>
21 * [20-19] : Op0
22 * [18-16] : Op1
23 * [15-12] : CRn
24 * [11-8] : CRm
25 * [7-5] : Op2
82 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
95 #define PSTATE_UAO pstate_field(0, 3)
96 #define PSTATE_SSBS pstate_field(3, 1)
97 #define PSTATE_DIT pstate_field(3, 2)
98 #define PSTATE_TCO pstate_field(3, 4)
112 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
116 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
117 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
118 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
119 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
120 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
121 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
122 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
123 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
124 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
132 #include "asm/sysreg-defs.h"
138 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
139 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
140 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
146 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
148 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
149 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
151 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
152 #define OSLSR_EL1_OSLK BIT(1)
154 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
155 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
159 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
160 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
161 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
162 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
165 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
166 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
167 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
169 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
170 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
171 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
173 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
175 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
177 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
178 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
179 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
180 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
182 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
183 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
184 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
185 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
187 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
188 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
190 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
191 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
193 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
195 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
196 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
197 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
199 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
200 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
201 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
202 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
203 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
204 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
205 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
206 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
207 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
208 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
210 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
213 #define SYS_PAR_EL1_FST GENMASK(6, 1)
238 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
239 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
241 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
243 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
244 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
246 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
247 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
249 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
250 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
251 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
252 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
253 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
255 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
257 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
258 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
260 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
262 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
263 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
264 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
265 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
266 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
267 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
268 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
269 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
270 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
271 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
272 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
273 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
274 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
275 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
277 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
279 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
281 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
282 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
284 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
285 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
286 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
287 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
288 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
289 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
290 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
291 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
292 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
293 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
294 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
295 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
296 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
298 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
299 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
300 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
302 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
305 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
307 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
309 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
312 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
313 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
318 * Counter: 11 011 1101 010:n<3> n<2:0>
319 * Type: 11 011 1101 011:n<3> n<2:0>
320 * n: 0-15
322 * Group 1 of activity monitors (auxiliary):
324 * Counter: 11 011 1101 110:n<3> n<2:0>
325 * Type: 11 011 1101 111:n<3> n<2:0>
326 * n: 0-15
329 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
330 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
331 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
332 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
336 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
338 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
340 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
342 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
343 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
344 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
346 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
347 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
348 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
350 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
351 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
354 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
360 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
361 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
362 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
363 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
365 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
367 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
368 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
370 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
371 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
372 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
373 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
374 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
375 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
376 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
378 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
379 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
380 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
381 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
382 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
384 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
385 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
386 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
387 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
388 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
389 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
390 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
391 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
392 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
393 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
394 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
395 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
396 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
397 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
399 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
400 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
402 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
403 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
405 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
406 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
407 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
408 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
409 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
411 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
413 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
415 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
417 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
419 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
421 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
422 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
423 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
424 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
425 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
426 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
427 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
428 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
430 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
432 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
434 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
440 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
442 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
444 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
450 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
451 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
453 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
454 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
456 /* VHE encodings for architectural EL0/1 system registers */
457 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
458 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
459 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
460 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
461 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
462 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
463 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
464 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
465 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
466 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
467 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
468 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
469 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
470 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
471 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
472 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
473 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
474 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
475 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
476 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
478 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
502 #define SCTLR_ELx_SA (BIT(3))
504 #define SCTLR_ELx_A (BIT(1))
622 #define SYS_TFSR_EL1_TF1_SHIFT 1
623 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
624 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
634 #define TRFCR_EL2_CX BIT(3)
635 #define TRFCR_ELx_ExTRE BIT(1)
640 #define ICH_MISR_EOI (1 << 0)
641 #define ICH_MISR_U (1 << 1)
644 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
646 #define ICH_LR_EOI (1ULL << 41)
647 #define ICH_LR_GROUP (1ULL << 60)
648 #define ICH_LR_HW (1ULL << 61)
649 #define ICH_LR_STATE (3ULL << 62)
650 #define ICH_LR_PENDING_BIT (1ULL << 62)
651 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
658 #define ICH_HCR_EN (1 << 0)
659 #define ICH_HCR_UIE (1 << 1)
660 #define ICH_HCR_NPIE (1 << 3)
661 #define ICH_HCR_TC (1 << 10)
662 #define ICH_HCR_TALL0 (1 << 11)
663 #define ICH_HCR_TALL1 (1 << 12)
664 #define ICH_HCR_TDIR (1 << 14)
670 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
671 #define ICH_VMCR_FIQ_EN_SHIFT 3
672 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
674 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
676 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
684 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
685 #define ICH_VMCR_ENG1_SHIFT 1
686 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
694 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
696 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
698 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
806 * set mask are set. Other bits are left as-is.