Lines Matching +full:i2s +full:- +full:regs
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xtfpga I2S controller driver
17 #define DRV_NAME "xtfpga-i2s"
46 * I2S controller operation:
61 void __iomem *regs;
69 * read-side critical section. Trigger callback sets and clears the
76 unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
123 * xtfpga_pcm_tx_2x16 for 16-bit stereo.
125 * FIFO consists of 32-bit words, one word per channel, always 2 channels.
126 * If I2S interface is configured with smaller sample resolution, only
131 struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
135 (void *)runtime->dma_area; \
137 for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
138 i2s->tx_fifo_level += 2) { \
140 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
141 iowrite32(p[tx_ptr][channels - 1], \
142 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
143 if (++tx_ptr >= runtime->buffer_size) \
156 static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
162 tx_substream = rcu_dereference(i2s->tx_substream);
165 unsigned tx_ptr = READ_ONCE(i2s->tx_ptr);
166 unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
169 cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
176 static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
181 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
185 bool tx_active = xtfpga_pcm_push_tx(i2s);
187 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
190 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
201 i2s->tx_fifo_level = i2s->tx_fifo_low;
205 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
208 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
212 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
218 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
225 struct xtfpga_i2s *i2s = dev_id;
229 regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
230 regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
231 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
241 i2s->tx_fifo_level = 0;
242 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
248 i2s->tx_fifo_level = i2s->tx_fifo_low;
252 tx_substream = rcu_dereference(i2s->tx_substream);
257 dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
265 xtfpga_pcm_refill_fifo(i2s);
273 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
275 snd_soc_dai_set_dma_data(dai, substream, i2s);
283 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
291 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
296 err = clk_set_rate(i2s->clk, freq);
300 /* ratio field of the config register controls MCLK->I2S clock
301 * derivation: I2S clock = MCLK / (2 * (ratio + 2)).
306 ratio = (freq - (srate * sample_size * 8)) /
309 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
313 i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
317 i2s->tx_fifo_low / 2 >= period_size * 2 &&
320 i2s->tx_fifo_low /= 2;
322 i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
324 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
328 dev_dbg(i2s->dev,
331 dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
341 return -EINVAL;
343 return -EINVAL;
345 return -EINVAL;
371 struct snd_pcm_runtime *runtime = substream->runtime;
377 runtime->private_data = p;
393 struct snd_pcm_runtime *runtime = substream->runtime;
394 struct xtfpga_i2s *i2s = runtime->private_data;
403 return -EINVAL;
409 i2s->tx_fn = (channels == 1) ?
415 i2s->tx_fn = (channels == 1) ?
421 return -EINVAL;
431 struct snd_pcm_runtime *runtime = substream->runtime;
432 struct xtfpga_i2s *i2s = runtime->private_data;
438 WRITE_ONCE(i2s->tx_ptr, 0);
439 rcu_assign_pointer(i2s->tx_substream, substream);
440 xtfpga_pcm_refill_fifo(i2s);
446 rcu_assign_pointer(i2s->tx_substream, NULL);
450 ret = -EINVAL;
459 struct snd_pcm_runtime *runtime = substream->runtime;
460 struct xtfpga_i2s *i2s = runtime->private_data;
461 snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);
463 return pos < runtime->buffer_size ? pos : 0;
469 struct snd_card *card = rtd->card->snd_card;
472 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
473 card->dev, size, size);
496 .name = "xtfpga-i2s",
511 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
513 clk_disable_unprepare(i2s->clk);
519 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
522 ret = clk_prepare_enable(i2s->clk);
532 struct xtfpga_i2s *i2s;
535 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
536 if (!i2s) {
537 err = -ENOMEM;
540 platform_set_drvdata(pdev, i2s);
541 i2s->dev = &pdev->dev;
542 dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
544 i2s->regs = devm_platform_ioremap_resource(pdev, 0);
545 if (IS_ERR(i2s->regs)) {
546 err = PTR_ERR(i2s->regs);
550 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
552 if (IS_ERR(i2s->regmap)) {
553 dev_err(&pdev->dev, "regmap init failed\n");
554 err = PTR_ERR(i2s->regmap);
558 i2s->clk = devm_clk_get(&pdev->dev, NULL);
559 if (IS_ERR(i2s->clk)) {
560 dev_err(&pdev->dev, "couldn't get clock\n");
561 err = PTR_ERR(i2s->clk);
565 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
567 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
568 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
575 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
578 pdev->name, i2s);
580 dev_err(&pdev->dev, "request_irq failed\n");
584 err = devm_snd_soc_register_component(&pdev->dev,
589 dev_err(&pdev->dev, "couldn't register component\n");
593 pm_runtime_enable(&pdev->dev);
594 if (!pm_runtime_enabled(&pdev->dev)) {
595 err = xtfpga_i2s_runtime_resume(&pdev->dev);
602 pm_runtime_disable(&pdev->dev);
604 dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
610 struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
612 if (i2s->regmap && !IS_ERR(i2s->regmap)) {
613 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
614 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
615 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
618 pm_runtime_disable(&pdev->dev);
619 if (!pm_runtime_status_suspended(&pdev->dev))
620 xtfpga_i2s_runtime_suspend(&pdev->dev);
625 { .compatible = "cdns,xtfpga-i2s", },
640 .name = "xtfpga-i2s",
649 MODULE_DESCRIPTION("xtfpga I2S controller driver");