1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (c) 2016-2018 Socionext Inc.
17 #include "aio-reg.h"
22 		return wr - rd;  in rb_cnt()
24 		return len - (rd - wr);  in rb_cnt()
30 		return wr - rd;  in rb_cnt_to_end()
32 		return len - rd;  in rb_cnt_to_end()
38 		return len - (wr - rd) - 8;  in rb_space()
40 		return rd - wr - 8;  in rb_space()
46 		return rd - wr - 8;  in rb_space_to_end()
48 		return len - wr;  in rb_space_to_end()
50 		return len - wr - 8;  in rb_space_to_end()
53 u64 aio_rb_cnt(struct uniphier_aio_sub *sub)  in aio_rb_cnt()  argument
55 	return rb_cnt(sub->wr_offs, sub->rd_offs, sub->compr_bytes);  in aio_rb_cnt()
58 u64 aio_rbt_cnt_to_end(struct uniphier_aio_sub *sub)  in aio_rbt_cnt_to_end()  argument
60 	return rb_cnt_to_end(sub->wr_offs, sub->rd_offs, sub->compr_bytes);  in aio_rbt_cnt_to_end()
63 u64 aio_rb_space(struct uniphier_aio_sub *sub)  in aio_rb_space()  argument
65 	return rb_space(sub->wr_offs, sub->rd_offs, sub->compr_bytes);  in aio_rb_space()
68 u64 aio_rb_space_to_end(struct uniphier_aio_sub *sub)  in aio_rb_space_to_end()  argument
70 	return rb_space_to_end(sub->wr_offs, sub->rd_offs, sub->compr_bytes);  in aio_rb_space_to_end()
74  * aio_iecout_set_enable - setup IEC output via SoC glue
86 	struct regmap *r = chip->regmap_sg;  in aio_iecout_set_enable()
95  * aio_chip_set_pll - set frequency to audio PLL
108 	struct device *dev = &chip->pdev->dev;  in aio_chip_set_pll()
109 	struct regmap *r = chip->regmap;  in aio_chip_set_pll()
132 		return -EINVAL;  in aio_chip_set_pll()
144 		return -EINVAL;  in aio_chip_set_pll()
146 	chip->plls[pll_id].freq = freq;  in aio_chip_set_pll()
155  * aio_chip_init - initialize AIO whole settings
167 	struct regmap *r = chip->regmap;  in aio_chip_init()
183 	if (chip->chip_spec->addr_ext)  in aio_chip_init()
192  * aio_init - initialize AIO substream
193  * @sub: the AIO substream pointer
200 int aio_init(struct uniphier_aio_sub *sub)  in aio_init()  argument
202 	struct device *dev = &sub->aio->chip->pdev->dev;  in aio_init()
203 	struct regmap *r = sub->aio->chip->regmap;  in aio_init()
205 	regmap_write(r, A2RBNMAPCTR0(sub->swm->rb.hw),  in aio_init()
206 		     MAPCTR0_EN | sub->swm->rb.map);  in aio_init()
207 	regmap_write(r, A2CHNMAPCTR0(sub->swm->ch.hw),  in aio_init()
208 		     MAPCTR0_EN | sub->swm->ch.map);  in aio_init()
210 	switch (sub->swm->type) {  in aio_init()
214 		if (sub->swm->dir == PORT_DIR_INPUT) {  in aio_init()
215 			regmap_write(r, A2IIFNMAPCTR0(sub->swm->iif.hw),  in aio_init()
216 				     MAPCTR0_EN | sub->swm->iif.map);  in aio_init()
217 			regmap_write(r, A2IPORTNMAPCTR0(sub->swm->iport.hw),  in aio_init()
218 				     MAPCTR0_EN | sub->swm->iport.map);  in aio_init()
220 			regmap_write(r, A2OIFNMAPCTR0(sub->swm->oif.hw),  in aio_init()
221 				     MAPCTR0_EN | sub->swm->oif.map);  in aio_init()
222 			regmap_write(r, A2OPORTNMAPCTR0(sub->swm->oport.hw),  in aio_init()
223 				     MAPCTR0_EN | sub->swm->oport.map);  in aio_init()
227 		regmap_write(r, A2OIFNMAPCTR0(sub->swm->oif.hw),  in aio_init()
228 			     MAPCTR0_EN | sub->swm->oif.map);  in aio_init()
229 		regmap_write(r, A2OPORTNMAPCTR0(sub->swm->oport.hw),  in aio_init()
230 			     MAPCTR0_EN | sub->swm->oport.map);  in aio_init()
231 		regmap_write(r, A2CHNMAPCTR0(sub->swm->och.hw),  in aio_init()
232 			     MAPCTR0_EN | sub->swm->och.map);  in aio_init()
233 		regmap_write(r, A2IIFNMAPCTR0(sub->swm->iif.hw),  in aio_init()
234 			     MAPCTR0_EN | sub->swm->iif.map);  in aio_init()
237 		dev_err(dev, "Unknown port type %d.\n", sub->swm->type);  in aio_init()
238 		return -EINVAL;  in aio_init()
245  * aio_port_reset - reset AIO port block
246  * @sub: the AIO substream pointer
248  * Resets the digital signal input/output port block of AIO.
250 void aio_port_reset(struct uniphier_aio_sub *sub)  in aio_port_reset()  argument
252 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_reset()
254 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aio_port_reset()
255 		regmap_write(r, AOUTRSTCTR0, BIT(sub->swm->oport.map));  in aio_port_reset()
256 		regmap_write(r, AOUTRSTCTR1, BIT(sub->swm->oport.map));  in aio_port_reset()
258 		regmap_update_bits(r, IPORTMXRSTCTR(sub->swm->iport.map),  in aio_port_reset()
261 		regmap_update_bits(r, IPORTMXRSTCTR(sub->swm->iport.map),  in aio_port_reset()
268  * aio_port_set_ch - set channels of LPCM
269  * @sub: the AIO substream pointer, PCM substream only
271  * Set suitable slot selecting to input/output port block of AIO.
273  * This function may return error if non-PCM substream.
277 static int aio_port_set_ch(struct uniphier_aio_sub *sub)  in aio_port_set_ch()  argument
279 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_set_ch()
294 	switch (params_channels(&sub->params)) {  in aio_port_set_ch()
305 		return -EINVAL;  in aio_port_set_ch()
309 		regmap_update_bits(r, OPORTMXTYSLOTCTR(sub->swm->oport.map, i),  in aio_port_set_ch()
311 		regmap_update_bits(r, OPORTMXTYSLOTCTR(sub->swm->oport.map, i),  in aio_port_set_ch()
319  * aio_port_set_rate - set sampling rate of LPCM
320  * @sub: the AIO substream pointer, PCM substream only
323  * Set suitable I2S format settings to input/output port block of AIO.
326  * This function may return error if non-PCM substream.
330 static int aio_port_set_rate(struct uniphier_aio_sub *sub, int rate)  in aio_port_set_rate()  argument
332 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_set_rate()
333 	struct device *dev = &sub->aio->chip->pdev->dev;  in aio_port_set_rate()
336 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aio_port_set_rate()
379 			return -EINVAL;  in aio_port_set_rate()
382 		regmap_update_bits(r, OPORTMXCTR1(sub->swm->oport.map),  in aio_port_set_rate()
427 			return -EINVAL;  in aio_port_set_rate()
430 		regmap_update_bits(r, IPORTMXCTR1(sub->swm->iport.map),  in aio_port_set_rate()
438  * aio_port_set_fmt - set format of I2S data
439  * @sub: the AIO substream pointer, PCM substream only
442  * Set suitable I2S format settings to input/output port block of AIO.
445  * This function may return error if non-PCM substream.
449 static int aio_port_set_fmt(struct uniphier_aio_sub *sub)  in aio_port_set_fmt()  argument
451 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_set_fmt()
452 	struct device *dev = &sub->aio->chip->pdev->dev;  in aio_port_set_fmt()
455 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aio_port_set_fmt()
456 		switch (sub->aio->fmt) {  in aio_port_set_fmt()
468 				sub->aio->fmt);  in aio_port_set_fmt()
469 			return -EINVAL;  in aio_port_set_fmt()
473 		regmap_update_bits(r, OPORTMXCTR1(sub->swm->oport.map),  in aio_port_set_fmt()
477 		switch (sub->aio->fmt) {  in aio_port_set_fmt()
489 				sub->aio->fmt);  in aio_port_set_fmt()
490 			return -EINVAL;  in aio_port_set_fmt()
495 		regmap_update_bits(r, IPORTMXCTR1(sub->swm->iport.map),  in aio_port_set_fmt()
505  * aio_port_set_clk - set clock and divider of AIO port block
506  * @sub: the AIO substream pointer
509  * input/output port block of AIO. Parameters are specified by
514 static int aio_port_set_clk(struct uniphier_aio_sub *sub)  in aio_port_set_clk()  argument
516 	struct uniphier_aio_chip *chip = sub->aio->chip;  in aio_port_set_clk()
517 	struct device *dev = &sub->aio->chip->pdev->dev;  in aio_port_set_clk()
518 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_set_clk()
531 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aio_port_set_clk()
532 		if (sub->swm->type == PORT_TYPE_I2S) {  in aio_port_set_clk()
533 			if (sub->aio->pll_out >= ARRAY_SIZE(v_pll)) {  in aio_port_set_clk()
535 					sub->aio->pll_out);  in aio_port_set_clk()
536 				return -EINVAL;  in aio_port_set_clk()
538 			if (sub->aio->plldiv >= ARRAY_SIZE(v_div)) {  in aio_port_set_clk()
540 					sub->aio->plldiv);  in aio_port_set_clk()
541 				return -EINVAL;  in aio_port_set_clk()
544 			v = v_pll[sub->aio->pll_out] |  in aio_port_set_clk()
546 				v_div[sub->aio->plldiv];  in aio_port_set_clk()
548 			switch (chip->plls[sub->aio->pll_out].freq) {  in aio_port_set_clk()
558 		} else if (sub->swm->type == PORT_TYPE_EVE) {  in aio_port_set_clk()
563 		} else if (sub->swm->type == PORT_TYPE_SPDIF) {  in aio_port_set_clk()
564 			if (sub->aio->pll_out >= ARRAY_SIZE(v_pll)) {  in aio_port_set_clk()
566 					sub->aio->pll_out);  in aio_port_set_clk()
567 				return -EINVAL;  in aio_port_set_clk()
569 			v = v_pll[sub->aio->pll_out] |  in aio_port_set_clk()
573 			switch (chip->plls[sub->aio->pll_out].freq) {  in aio_port_set_clk()
589 		regmap_write(r, OPORTMXCTR2(sub->swm->oport.map), v);  in aio_port_set_clk()
595 		regmap_write(r, IPORTMXCTR2(sub->swm->iport.map), v);  in aio_port_set_clk()
602  * aio_port_set_param - set parameters of AIO port block
603  * @sub: the AIO substream pointer
608  * Set suitable setting to input/output port block of AIO to process the
613 int aio_port_set_param(struct uniphier_aio_sub *sub, int pass_through,  in aio_port_set_param()  argument
616 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_set_param()
622 		if (sub->swm->type == PORT_TYPE_EVE ||  in aio_port_set_param()
623 		    sub->swm->type == PORT_TYPE_CONV) {  in aio_port_set_param()
629 		ret = aio_port_set_ch(sub);  in aio_port_set_param()
633 		ret = aio_port_set_rate(sub, rate);  in aio_port_set_param()
637 		ret = aio_port_set_fmt(sub);  in aio_port_set_param()
642 	ret = aio_port_set_clk(sub);  in aio_port_set_param()
646 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aio_port_set_param()
657 		regmap_write(r, OPORTMXCTR3(sub->swm->oport.map), v);  in aio_port_set_param()
659 		regmap_write(r, IPORTMXACLKSEL0EX(sub->swm->iport.map),  in aio_port_set_param()
661 		regmap_write(r, IPORTMXEXNOE(sub->swm->iport.map),  in aio_port_set_param()
669  * aio_port_set_enable - start or stop of AIO port block
670  * @sub: the AIO substream pointer
671  * @enable: zero to stop the block, otherwise to start
673  * Start or stop the signal input/output port block of AIO.
675 void aio_port_set_enable(struct uniphier_aio_sub *sub, int enable)  in aio_port_set_enable()  argument
677 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_set_enable()
679 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aio_port_set_enable()
680 		regmap_write(r, OPORTMXPATH(sub->swm->oport.map),  in aio_port_set_enable()
681 			     sub->swm->oif.map);  in aio_port_set_enable()
683 		regmap_update_bits(r, OPORTMXMASK(sub->swm->oport.map),  in aio_port_set_enable()
694 			regmap_write(r, AOUTENCTR0, BIT(sub->swm->oport.map));  in aio_port_set_enable()
696 			regmap_write(r, AOUTENCTR1, BIT(sub->swm->oport.map));  in aio_port_set_enable()
698 		regmap_update_bits(r, IPORTMXMASK(sub->swm->iport.map),  in aio_port_set_enable()
706 					   IPORTMXCTR2(sub->swm->iport.map),  in aio_port_set_enable()
711 					   IPORTMXCTR2(sub->swm->iport.map),  in aio_port_set_enable()
718  * aio_port_get_volume - get volume of AIO port block
719  * @sub: the AIO substream pointer
721  * Return: current volume, range is 0x0000 - 0xffff
723 int aio_port_get_volume(struct uniphier_aio_sub *sub)  in aio_port_get_volume()  argument
725 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_get_volume()
728 	regmap_read(r, OPORTMXTYVOLGAINSTATUS(sub->swm->oport.map, 0), &v);  in aio_port_get_volume()
734  * aio_port_set_volume - set volume of AIO port block
735  * @sub: the AIO substream pointer
736  * @vol: target volume, range is 0x0000 - 0xffff.
738  * Change digital volume and perfome fade-out/fade-in effect for specified
742 void aio_port_set_volume(struct uniphier_aio_sub *sub, int vol)  in aio_port_set_volume()  argument
744 	struct regmap *r = sub->aio->chip->regmap;  in aio_port_set_volume()
745 	int oport_map = sub->swm->oport.map;  in aio_port_set_volume()
748 	if (sub->swm->dir == PORT_DIR_INPUT)  in aio_port_set_volume()
751 	cur = aio_port_get_volume(sub);  in aio_port_set_volume()
752 	diff = abs(vol - cur);  in aio_port_set_volume()
753 	fs = params_rate(&sub->params);  in aio_port_set_volume()
776  * aio_if_set_param - set parameters of AIO DMA I/F block
777  * @sub: the AIO substream pointer
781  * Set suitable setting to DMA interface block of AIO to process the
786 int aio_if_set_param(struct uniphier_aio_sub *sub, int pass_through)  in aio_if_set_param()  argument
788 	struct regmap *r = sub->aio->chip->regmap;  in aio_if_set_param()
791 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aio_if_set_param()
796 			switch (params_channels(&sub->params)) {  in aio_if_set_param()
807 				return -EINVAL;  in aio_if_set_param()
812 		regmap_write(r, PBOUTMXCTR0(sub->swm->oif.map), v);  in aio_if_set_param()
813 		regmap_write(r, PBOUTMXCTR1(sub->swm->oif.map), 0);  in aio_if_set_param()
815 		regmap_write(r, PBINMXCTR(sub->swm->iif.map),  in aio_if_set_param()
818 			     (sub->swm->iport.map << PBINMXCTR_PBINSEL_SHIFT) |  in aio_if_set_param()
827  * aio_oport_set_stream_type - set parameters of AIO playback port block
828  * @sub: the AIO substream pointer
831  * Set special setting to output port block of AIO to output the stream
836 int aio_oport_set_stream_type(struct uniphier_aio_sub *sub,  in aio_oport_set_stream_type()  argument
839 	struct regmap *r = sub->aio->chip->regmap;  in aio_oport_set_stream_type()
883 	regmap_write(r, OPORTMXREPET(sub->swm->oport.map), repet);  in aio_oport_set_stream_type()
884 	regmap_write(r, OPORTMXPAUDAT(sub->swm->oport.map), pause);  in aio_oport_set_stream_type()
890  * aio_src_reset - reset AIO SRC block
891  * @sub: the AIO substream pointer
894  * block of AIO.
897 void aio_src_reset(struct uniphier_aio_sub *sub)  in aio_src_reset()  argument
899 	struct regmap *r = sub->aio->chip->regmap;  in aio_src_reset()
901 	if (sub->swm->dir != PORT_DIR_OUTPUT)  in aio_src_reset()
904 	regmap_write(r, AOUTSRCRSTCTR0, BIT(sub->swm->oport.map));  in aio_src_reset()
905 	regmap_write(r, AOUTSRCRSTCTR1, BIT(sub->swm->oport.map));  in aio_src_reset()
909  * aio_src_set_param - set parameters of AIO SRC block
910  * @sub: the AIO substream pointer
914  * block of AIO to process the specified in params.
919 int aio_src_set_param(struct uniphier_aio_sub *sub,  in aio_src_set_param()  argument
922 	struct regmap *r = sub->aio->chip->regmap;  in aio_src_set_param()
925 	if (sub->swm->dir != PORT_DIR_OUTPUT)  in aio_src_set_param()
928 	regmap_write(r, OPORTMXSRC1CTR(sub->swm->oport.map),  in aio_src_set_param()
954 	regmap_write(r, OPORTMXRATE_I(sub->swm->oport.map),  in aio_src_set_param()
957 	regmap_update_bits(r, OPORTMXRATE_I(sub->swm->oport.map),  in aio_src_set_param()
964 int aio_srcif_set_param(struct uniphier_aio_sub *sub)  in aio_srcif_set_param()  argument
966 	struct regmap *r = sub->aio->chip->regmap;  in aio_srcif_set_param()
968 	regmap_write(r, PBINMXCTR(sub->swm->iif.map),  in aio_srcif_set_param()
971 		     (sub->swm->oport.map << PBINMXCTR_PBINSEL_SHIFT) |  in aio_srcif_set_param()
978 int aio_srcch_set_param(struct uniphier_aio_sub *sub)  in aio_srcch_set_param()  argument
980 	struct regmap *r = sub->aio->chip->regmap;  in aio_srcch_set_param()
982 	regmap_write(r, CDA2D_CHMXCTRL1(sub->swm->och.map),  in aio_srcch_set_param()
985 	regmap_write(r, CDA2D_CHMXSRCAMODE(sub->swm->och.map),  in aio_srcch_set_param()
990 	regmap_write(r, CDA2D_CHMXDSTAMODE(sub->swm->och.map),  in aio_srcch_set_param()
994 		     (sub->swm->och.map << CDA2D_CHMXAMODE_RSSEL_SHIFT));  in aio_srcch_set_param()
999 void aio_srcch_set_enable(struct uniphier_aio_sub *sub, int enable)  in aio_srcch_set_enable()  argument
1001 	struct regmap *r = sub->aio->chip->regmap;  in aio_srcch_set_enable()
1010 		     v | BIT(sub->swm->och.map));  in aio_srcch_set_enable()
1013 int aiodma_ch_set_param(struct uniphier_aio_sub *sub)  in aiodma_ch_set_param()  argument
1015 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_ch_set_param()
1018 	regmap_write(r, CDA2D_CHMXCTRL1(sub->swm->ch.map),  in aiodma_ch_set_param()
1024 		(sub->swm->rb.map << CDA2D_CHMXAMODE_RSSEL_SHIFT);  in aiodma_ch_set_param()
1025 	if (sub->swm->dir == PORT_DIR_OUTPUT)  in aiodma_ch_set_param()
1026 		regmap_write(r, CDA2D_CHMXSRCAMODE(sub->swm->ch.map), v);  in aiodma_ch_set_param()
1028 		regmap_write(r, CDA2D_CHMXDSTAMODE(sub->swm->ch.map), v);  in aiodma_ch_set_param()
1033 void aiodma_ch_set_enable(struct uniphier_aio_sub *sub, int enable)  in aiodma_ch_set_enable()  argument
1035 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_ch_set_enable()
1039 			     CDA2D_STRT0_STOP_START | BIT(sub->swm->ch.map));  in aiodma_ch_set_enable()
1042 				   BIT(sub->swm->rb.map),  in aiodma_ch_set_enable()
1043 				   BIT(sub->swm->rb.map));  in aiodma_ch_set_enable()
1046 			     CDA2D_STRT0_STOP_STOP | BIT(sub->swm->ch.map));  in aiodma_ch_set_enable()
1049 				   BIT(sub->swm->rb.map),  in aiodma_ch_set_enable()
1054 static u64 aiodma_rb_get_rp(struct uniphier_aio_sub *sub)  in aiodma_rb_get_rp()  argument
1056 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_rb_get_rp()
1061 		     CDA2D_RDPTRLOAD_LSFLAG_STORE | BIT(sub->swm->rb.map));  in aiodma_rb_get_rp()
1064 		regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &pos_l);  in aiodma_rb_get_rp()
1066 	regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &pos_l);  in aiodma_rb_get_rp()
1067 	regmap_read(r, CDA2D_RBMXRDPTRU(sub->swm->rb.map), &pos_u);  in aiodma_rb_get_rp()
1073 static void aiodma_rb_set_rp(struct uniphier_aio_sub *sub, u64 pos)  in aiodma_rb_set_rp()  argument
1075 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_rb_set_rp()
1079 	regmap_write(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), (u32)pos);  in aiodma_rb_set_rp()
1080 	regmap_write(r, CDA2D_RBMXRDPTRU(sub->swm->rb.map), (u32)(pos >> 32));  in aiodma_rb_set_rp()
1081 	regmap_write(r, CDA2D_RDPTRLOAD, BIT(sub->swm->rb.map));  in aiodma_rb_set_rp()
1084 		regmap_read(r, CDA2D_RBMXRDPTR(sub->swm->rb.map), &tmp);  in aiodma_rb_set_rp()
1087 static u64 aiodma_rb_get_wp(struct uniphier_aio_sub *sub)  in aiodma_rb_get_wp()  argument
1089 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_rb_get_wp()
1094 		     CDA2D_WRPTRLOAD_LSFLAG_STORE | BIT(sub->swm->rb.map));  in aiodma_rb_get_wp()
1097 		regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &pos_l);  in aiodma_rb_get_wp()
1099 	regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &pos_l);  in aiodma_rb_get_wp()
1100 	regmap_read(r, CDA2D_RBMXWRPTRU(sub->swm->rb.map), &pos_u);  in aiodma_rb_get_wp()
1106 static void aiodma_rb_set_wp(struct uniphier_aio_sub *sub, u64 pos)  in aiodma_rb_set_wp()  argument
1108 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_rb_set_wp()
1112 	regmap_write(r, CDA2D_RBMXWRPTR(sub->swm->rb.map),  in aiodma_rb_set_wp()
1114 	regmap_write(r, CDA2D_RBMXWRPTRU(sub->swm->rb.map),  in aiodma_rb_set_wp()
1116 	regmap_write(r, CDA2D_WRPTRLOAD, BIT(sub->swm->rb.map));  in aiodma_rb_set_wp()
1119 		regmap_read(r, CDA2D_RBMXWRPTR(sub->swm->rb.map), &tmp);  in aiodma_rb_set_wp()
1122 int aiodma_rb_set_threshold(struct uniphier_aio_sub *sub, u64 size, u32 th)  in aiodma_rb_set_threshold()  argument
1124 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_rb_set_threshold()
1127 		return -EINVAL;  in aiodma_rb_set_threshold()
1129 	regmap_write(r, CDA2D_RBMXBTH(sub->swm->rb.map), th);  in aiodma_rb_set_threshold()
1130 	regmap_write(r, CDA2D_RBMXRTH(sub->swm->rb.map), th);  in aiodma_rb_set_threshold()
1135 int aiodma_rb_set_buffer(struct uniphier_aio_sub *sub, u64 start, u64 end,  in aiodma_rb_set_buffer()  argument
1138 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_rb_set_buffer()
1139 	u64 size = end - start;  in aiodma_rb_set_buffer()
1143 		return -EINVAL;  in aiodma_rb_set_buffer()
1145 	regmap_write(r, CDA2D_RBMXCNFG(sub->swm->rb.map), 0);  in aiodma_rb_set_buffer()
1146 	regmap_write(r, CDA2D_RBMXBGNADRS(sub->swm->rb.map),  in aiodma_rb_set_buffer()
1148 	regmap_write(r, CDA2D_RBMXBGNADRSU(sub->swm->rb.map),  in aiodma_rb_set_buffer()
1150 	regmap_write(r, CDA2D_RBMXENDADRS(sub->swm->rb.map),  in aiodma_rb_set_buffer()
1152 	regmap_write(r, CDA2D_RBMXENDADRSU(sub->swm->rb.map),  in aiodma_rb_set_buffer()
1155 	regmap_write(r, CDA2D_RBADRSLOAD, BIT(sub->swm->rb.map));  in aiodma_rb_set_buffer()
1157 	ret = aiodma_rb_set_threshold(sub, size, 2 * period);  in aiodma_rb_set_buffer()
1161 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aiodma_rb_set_buffer()
1162 		aiodma_rb_set_rp(sub, start);  in aiodma_rb_set_buffer()
1163 		aiodma_rb_set_wp(sub, end - period);  in aiodma_rb_set_buffer()
1165 		regmap_update_bits(r, CDA2D_RBMXIE(sub->swm->rb.map),  in aiodma_rb_set_buffer()
1169 		aiodma_rb_set_rp(sub, end - period);  in aiodma_rb_set_buffer()
1170 		aiodma_rb_set_wp(sub, start);  in aiodma_rb_set_buffer()
1172 		regmap_update_bits(r, CDA2D_RBMXIE(sub->swm->rb.map),  in aiodma_rb_set_buffer()
1177 	sub->threshold = 2 * period;  in aiodma_rb_set_buffer()
1178 	sub->rd_offs = 0;  in aiodma_rb_set_buffer()
1179 	sub->wr_offs = 0;  in aiodma_rb_set_buffer()
1180 	sub->rd_org = 0;  in aiodma_rb_set_buffer()
1181 	sub->wr_org = 0;  in aiodma_rb_set_buffer()
1182 	sub->rd_total = 0;  in aiodma_rb_set_buffer()
1183 	sub->wr_total = 0;  in aiodma_rb_set_buffer()
1188 void aiodma_rb_sync(struct uniphier_aio_sub *sub, u64 start, u64 size,  in aiodma_rb_sync()  argument
1191 	if (sub->swm->dir == PORT_DIR_OUTPUT) {  in aiodma_rb_sync()
1192 		sub->rd_offs = aiodma_rb_get_rp(sub) - start;  in aiodma_rb_sync()
1194 		if (sub->use_mmap) {  in aiodma_rb_sync()
1195 			sub->threshold = 2 * period;  in aiodma_rb_sync()
1196 			aiodma_rb_set_threshold(sub, size, 2 * period);  in aiodma_rb_sync()
1198 			sub->wr_offs = sub->rd_offs - period;  in aiodma_rb_sync()
1199 			if (sub->rd_offs < period)  in aiodma_rb_sync()
1200 				sub->wr_offs += size;  in aiodma_rb_sync()
1202 		aiodma_rb_set_wp(sub, sub->wr_offs + start);  in aiodma_rb_sync()
1204 		sub->wr_offs = aiodma_rb_get_wp(sub) - start;  in aiodma_rb_sync()
1206 		if (sub->use_mmap) {  in aiodma_rb_sync()
1207 			sub->threshold = 2 * period;  in aiodma_rb_sync()
1208 			aiodma_rb_set_threshold(sub, size, 2 * period);  in aiodma_rb_sync()
1210 			sub->rd_offs = sub->wr_offs - period;  in aiodma_rb_sync()
1211 			if (sub->wr_offs < period)  in aiodma_rb_sync()
1212 				sub->rd_offs += size;  in aiodma_rb_sync()
1214 		aiodma_rb_set_rp(sub, sub->rd_offs + start);  in aiodma_rb_sync()
1217 	sub->rd_total += sub->rd_offs - sub->rd_org;  in aiodma_rb_sync()
1218 	if (sub->rd_offs < sub->rd_org)  in aiodma_rb_sync()
1219 		sub->rd_total += size;  in aiodma_rb_sync()
1220 	sub->wr_total += sub->wr_offs - sub->wr_org;  in aiodma_rb_sync()
1221 	if (sub->wr_offs < sub->wr_org)  in aiodma_rb_sync()
1222 		sub->wr_total += size;  in aiodma_rb_sync()
1224 	sub->rd_org = sub->rd_offs;  in aiodma_rb_sync()
1225 	sub->wr_org = sub->wr_offs;  in aiodma_rb_sync()
1228 bool aiodma_rb_is_irq(struct uniphier_aio_sub *sub)  in aiodma_rb_is_irq()  argument
1230 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_rb_is_irq()
1233 	regmap_read(r, CDA2D_RBMXIR(sub->swm->rb.map), &ir);  in aiodma_rb_is_irq()
1235 	if (sub->swm->dir == PORT_DIR_OUTPUT)  in aiodma_rb_is_irq()
1241 void aiodma_rb_clear_irq(struct uniphier_aio_sub *sub)  in aiodma_rb_clear_irq()  argument
1243 	struct regmap *r = sub->aio->chip->regmap;  in aiodma_rb_clear_irq()
1245 	if (sub->swm->dir == PORT_DIR_OUTPUT)  in aiodma_rb_clear_irq()
1246 		regmap_write(r, CDA2D_RBMXIR(sub->swm->rb.map),  in aiodma_rb_clear_irq()
1249 		regmap_write(r, CDA2D_RBMXIR(sub->swm->rb.map),  in aiodma_rb_clear_irq()