41 	dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n", MCBSP_READ(mcbsp, DRR2));  in omap_mcbsp_dump_reg()
42 	dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n", MCBSP_READ(mcbsp, DRR1));  in omap_mcbsp_dump_reg()
43 	dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n", MCBSP_READ(mcbsp, DXR2));  in omap_mcbsp_dump_reg()
44 	dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n", MCBSP_READ(mcbsp, DXR1));  in omap_mcbsp_dump_reg()
45 	dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));  in omap_mcbsp_dump_reg()
46 	dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));  in omap_mcbsp_dump_reg()
47 	dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n", MCBSP_READ(mcbsp, RCR2));  in omap_mcbsp_dump_reg()
48 	dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n", MCBSP_READ(mcbsp, RCR1));  in omap_mcbsp_dump_reg()
49 	dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n", MCBSP_READ(mcbsp, XCR2));  in omap_mcbsp_dump_reg()
50 	dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n", MCBSP_READ(mcbsp, XCR1));  in omap_mcbsp_dump_reg()
51 	dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));  in omap_mcbsp_dump_reg()
52 	dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));  in omap_mcbsp_dump_reg()
53 	dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n", MCBSP_READ(mcbsp, PCR0));  in omap_mcbsp_dump_reg()
97 	irqst = MCBSP_READ(mcbsp, IRQST);  in omap_mcbsp_irq_handler()
138 	irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);  in omap_mcbsp_tx_irq_handler()
156 	irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);  in omap_mcbsp_rx_irq_handler()
265 	buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);  in omap_mcbsp_get_tx_delay()
280 	buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);  in omap_mcbsp_get_rx_delay()
282 	threshold = MCBSP_READ(mcbsp, THRSH1);  in omap_mcbsp_get_rx_delay()