Lines Matching +full:high +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
100 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
103 #define MCASP_FREE BIT(0)
104 #define MCASP_SOFT BIT(1)
107 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
108 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
109 * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode
110 * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode
122 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
124 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
125 #define VA BIT(2)
126 #define VB BIT(3)
129 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
132 #define TXSEL BIT(3)
136 #define TXORD BIT(15)
140 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
143 #define RXSEL BIT(3)
147 #define RXORD BIT(15)
151 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
153 #define FSXPOL BIT(0)
154 #define AFSXE BIT(1)
155 #define FSXDUR BIT(4)
159 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
161 #define FSRPOL BIT(0)
162 #define AFSRE BIT(1)
163 #define FSRDUR BIT(4)
167 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
170 #define ACLKXE BIT(5)
171 #define TX_ASYNC BIT(6)
172 #define ACLKXPOL BIT(7)
179 #define ACLKRE BIT(5)
180 #define RX_ASYNC BIT(6)
181 #define ACLKRPOL BIT(7)
185 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
189 #define AHCLKXPOL BIT(14)
190 #define AHCLKXE BIT(15)
194 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
198 #define AHCLKRPOL BIT(14)
199 #define AHCLKRE BIT(15)
203 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
211 #define TXSTATE BIT(4)
212 #define RXSTATE BIT(5)
217 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
219 #define LBEN BIT(0)
220 #define LBORD BIT(1)
224 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
229 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
234 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
236 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
237 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
238 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
239 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
240 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
241 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
242 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
243 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
244 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
245 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
248 * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
249 * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
251 #define XRERR BIT(8) /* Transmit/Receive error */
252 #define XRDATA BIT(5) /* Transmit/Receive data ready */
255 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
258 #define MUTEINPOL BIT(2)
259 #define MUTEINENA BIT(3)
260 #define MUTEIN BIT(4)
261 #define MUTER BIT(5)
262 #define MUTEX BIT(6)
263 #define MUTEFSR BIT(7)
264 #define MUTEFSX BIT(8)
265 #define MUTEBADCLKR BIT(9)
266 #define MUTEBADCLKX BIT(10)
267 #define MUTERXDMAERR BIT(11)
268 #define MUTETXDMAERR BIT(12)
271 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
273 #define RXDATADMADIS BIT(0)
276 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
278 #define TXDATADMADIS BIT(0)
281 * DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits
283 #define ROVRN BIT(0)
286 * DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits
288 #define XUNDRN BIT(0)
291 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
293 #define FIFO_ENABLE BIT(16)
298 /* Source of High-frequency transmit/receive clock */