158 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)  in mcasp_get_reg()  function
172 		if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)  in mcasp_set_ctl_reg()
176 	if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))  in mcasp_set_ctl_reg()
182 	u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);  in mcasp_is_synchronous()
183 	u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);  in mcasp_is_synchronous()
272 	while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&  in mcasp_start_tx()
371 	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);  in davinci_mcasp_tx_irq_handler()
402 	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);  in davinci_mcasp_rx_irq_handler()
1124 	u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);  in davinci_mcasp_calc_clk_div()
1175 	return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);  in davinci_mcasp_tx_delay()
1183 	return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);  in davinci_mcasp_rx_delay()
2148 	val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);  in davinci_mcasp_gpio_direction_out()
2177 	val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);  in davinci_mcasp_gpio_direction_in()
2194 	val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);  in davinci_mcasp_gpio_get()
2207 	val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);  in davinci_mcasp_gpio_get_direction()
2484 		context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);  in davinci_mcasp_runtime_suspend()
2488 		context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);  in davinci_mcasp_runtime_suspend()
2492 		context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);  in davinci_mcasp_runtime_suspend()
2496 		context->xrsr_regs[i] = mcasp_get_reg(mcasp,  in davinci_mcasp_runtime_suspend()