Lines Matching +full:i2s +full:- +full:tx +full:- +full:route
1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra30_i2s.c - Tegra30 I2S driver
6 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (c) 2009-2010, NVIDIA Corporation.
36 #define DRV_NAME "tegra30-i2s"
40 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
42 regcache_cache_only(i2s->regmap, true);
44 clk_disable_unprepare(i2s->clk_i2s);
51 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
54 ret = clk_prepare_enable(i2s->clk_i2s);
60 regcache_cache_only(i2s->regmap, false);
61 regcache_mark_dirty(i2s->regmap);
63 ret = regcache_sync(i2s->regmap);
70 clk_disable_unprepare(i2s->clk_i2s);
78 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
85 return -EINVAL;
96 return -EINVAL;
123 return -EINVAL;
126 pm_runtime_get_sync(dai->dev);
127 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
128 pm_runtime_put(dai->dev);
137 struct device *dev = dai->dev;
138 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
144 return -EINVAL;
153 return -EINVAL;
156 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
163 bitcnt = (i2sclock / (2 * srate)) - 1;
165 return -EINVAL;
167 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
169 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
178 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
191 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
199 i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
203 regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
208 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
210 tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
211 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
216 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
218 tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
219 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
223 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
225 tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
226 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
231 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
233 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
235 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
241 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
247 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
248 tegra30_i2s_start_playback(i2s);
250 tegra30_i2s_start_capture(i2s);
255 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
256 tegra30_i2s_stop_playback(i2s);
258 tegra30_i2s_stop_capture(i2s);
261 return -EINVAL;
271 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
274 dev_dbg(dai->dev, "%s: txmask=0x%08x rxmask=0x%08x slots=%d width=%d\n",
283 ((slots - 1) << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT);
285 pm_runtime_get_sync(dai->dev);
286 regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);
288 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL,
290 pm_runtime_put(dai->dev);
297 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
299 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
300 &i2s->capture_dma_data);
401 { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
402 { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
408 struct tegra30_i2s *i2s;
414 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
415 if (!i2s) {
416 ret = -ENOMEM;
419 dev_set_drvdata(&pdev->dev, i2s);
421 soc_data = of_device_get_match_data(&pdev->dev);
423 dev_err(&pdev->dev, "Error: No device match found\n");
424 ret = -ENODEV;
427 i2s->soc_data = soc_data;
429 i2s->dai = tegra30_i2s_dai_template;
430 i2s->dai.name = dev_name(&pdev->dev);
432 ret = of_property_read_u32_array(pdev->dev.of_node,
433 "nvidia,ahub-cif-ids", cif_ids,
438 i2s->playback_i2s_cif = cif_ids[0];
439 i2s->capture_i2s_cif = cif_ids[1];
441 i2s->clk_i2s = devm_clk_get(&pdev->dev, NULL);
442 if (IS_ERR(i2s->clk_i2s)) {
443 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
444 ret = PTR_ERR(i2s->clk_i2s);
454 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
456 if (IS_ERR(i2s->regmap)) {
457 dev_err(&pdev->dev, "regmap init failed\n");
458 ret = PTR_ERR(i2s->regmap);
461 regcache_cache_only(i2s->regmap, true);
463 pm_runtime_enable(&pdev->dev);
465 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
466 i2s->playback_dma_data.maxburst = 4;
467 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
468 i2s->playback_dma_chan,
469 sizeof(i2s->playback_dma_chan),
470 &i2s->playback_dma_data.addr);
472 dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
475 ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
476 i2s->playback_fifo_cif);
478 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
482 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
483 i2s->capture_dma_data.maxburst = 4;
484 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
485 i2s->capture_dma_chan,
486 sizeof(i2s->capture_dma_chan),
487 &i2s->capture_dma_data.addr);
489 dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
492 ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
493 i2s->capture_i2s_cif);
495 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
499 ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
500 &i2s->dai, 1);
502 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
503 ret = -ENOMEM;
507 ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
508 &i2s->dma_config, i2s->playback_dma_chan,
509 i2s->capture_dma_chan);
511 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
518 snd_soc_unregister_component(&pdev->dev);
520 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
522 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
524 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
526 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
528 pm_runtime_disable(&pdev->dev);
535 struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
537 tegra_pcm_platform_unregister(&pdev->dev);
538 snd_soc_unregister_component(&pdev->dev);
540 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
541 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
543 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
544 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
546 pm_runtime_disable(&pdev->dev);
567 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");