Lines Matching +full:tegra210 +full:- +full:mbdrc
1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_mbdrc.c - Tegra210 MBDRC driver
52 /* Default MBDRC parameters */
57 .filter_structure = 0, /* All-pass tree */
87 /* Band-0 */
88 961046798, -2030431983, 1073741824,
89 2030431983, -961046798,
90 /* Band-1 */
91 1030244425, -2099481453, 1073741824,
92 2099481453, -1030244425,
93 /* Band-2 */
94 1067169294, -2136327263, 1073741824,
95 2136327263, -1067169294,
96 /* Band-3 */
97 434951949, -1306567134, 1073741824,
98 1306567134, -434951949,
99 /* Band-4 */
100 780656019, -1605955641, 1073741824,
101 1605955641, -780656019,
102 /* Band-5 */
103 1024497031, -1817128152, 1073741824,
104 1817128152, -1024497031,
105 /* Band-6 */
108 /* Band-7 */
137 /* Band-0 */
138 -1005668963, 1073741824, 0,
140 /* Band-1 */
141 998437058, -2067742187, 1073741824,
142 2067742187, -998437058,
143 /* Band-2 */
144 1051963422, -2121153948, 1073741824,
145 2121153948, -1051963422,
146 /* Band-3 */
147 434951949, -1306567134, 1073741824,
148 1306567134, -434951949,
149 /* Band-4 */
150 780656019, -1605955641, 1073741824,
151 1605955641, -780656019,
152 /* Band-5 */
153 1024497031, -1817128152, 1073741824,
154 1817128152, -1024497031,
155 /* Band-6 */
158 /* Band-7 */
187 /* Band-0 */
190 /* Band-1 */
193 /* Band-2 */
196 /* Band-3 */
197 -619925131, 1073741824, 0,
199 /* Band-4 */
200 606839335, -1455425976, 1073741824,
201 1455425976, -606839335,
202 /* Band-5 */
203 917759617, -1724690840, 1073741824,
204 1724690840, -917759617,
205 /* Band-6 */
208 /* Band-7 */
237 (struct soc_mixer_control *)kcontrol->private_value; in tegra210_mbdrc_get()
242 regmap_read(ope->mbdrc_regmap, mc->reg, &val); in tegra210_mbdrc_get()
244 ucontrol->value.integer.value[0] = (val >> mc->shift) & mc->max; in tegra210_mbdrc_get()
253 (struct soc_mixer_control *)kcontrol->private_value; in tegra210_mbdrc_put()
256 unsigned int val = ucontrol->value.integer.value[0]; in tegra210_mbdrc_put()
259 val = val << mc->shift; in tegra210_mbdrc_put()
261 regmap_update_bits_check(ope->mbdrc_regmap, mc->reg, in tegra210_mbdrc_put()
262 (mc->max << mc->shift), val, &change); in tegra210_mbdrc_put()
272 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in tegra210_mbdrc_get_enum()
275 regmap_read(ope->mbdrc_regmap, e->reg, &val); in tegra210_mbdrc_get_enum()
277 ucontrol->value.enumerated.item[0] = (val >> e->shift_l) & e->mask; in tegra210_mbdrc_get_enum()
287 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in tegra210_mbdrc_put_enum()
292 if (ucontrol->value.enumerated.item[0] > e->items - 1) in tegra210_mbdrc_put_enum()
293 return -EINVAL; in tegra210_mbdrc_put_enum()
295 val = ucontrol->value.enumerated.item[0] << e->shift_l; in tegra210_mbdrc_put_enum()
296 mask = e->mask << e->shift_l; in tegra210_mbdrc_put_enum()
298 regmap_update_bits_check(ope->mbdrc_regmap, e->reg, mask, val, in tegra210_mbdrc_put_enum()
307 struct tegra_soc_bytes *params = (void *)kcontrol->private_value; in tegra210_mbdrc_band_params_get()
310 u32 *data = (u32 *)ucontrol->value.bytes.data; in tegra210_mbdrc_band_params_get()
311 u32 regs = params->soc.base; in tegra210_mbdrc_band_params_get()
312 u32 mask = params->soc.mask; in tegra210_mbdrc_band_params_get()
313 u32 shift = params->shift; in tegra210_mbdrc_band_params_get()
316 for (i = 0; i < params->soc.num_regs; i++, regs += cmpnt->val_bytes) { in tegra210_mbdrc_band_params_get()
317 regmap_read(ope->mbdrc_regmap, regs, &data[i]); in tegra210_mbdrc_band_params_get()
328 struct tegra_soc_bytes *params = (void *)kcontrol->private_value; in tegra210_mbdrc_band_params_put()
331 u32 *data = (u32 *)ucontrol->value.bytes.data; in tegra210_mbdrc_band_params_put()
332 u32 regs = params->soc.base; in tegra210_mbdrc_band_params_put()
333 u32 mask = params->soc.mask; in tegra210_mbdrc_band_params_put()
334 u32 shift = params->shift; in tegra210_mbdrc_band_params_put()
338 for (i = 0; i < params->soc.num_regs; i++, regs += cmpnt->val_bytes) { in tegra210_mbdrc_band_params_put()
341 regmap_update_bits_check(ope->mbdrc_regmap, regs, mask, in tegra210_mbdrc_band_params_put()
353 struct tegra_soc_bytes *params = (void *)kcontrol->private_value; in tegra210_mbdrc_threshold_get()
356 u32 *data = (u32 *)ucontrol->value.bytes.data; in tegra210_mbdrc_threshold_get()
357 u32 regs = params->soc.base; in tegra210_mbdrc_threshold_get()
358 u32 num_regs = params->soc.num_regs; in tegra210_mbdrc_threshold_get()
362 for (i = 0; i < num_regs; i += 4, regs += cmpnt->val_bytes) { in tegra210_mbdrc_threshold_get()
363 regmap_read(ope->mbdrc_regmap, regs, &val); in tegra210_mbdrc_threshold_get()
381 struct tegra_soc_bytes *params = (void *)kcontrol->private_value; in tegra210_mbdrc_threshold_put()
384 u32 *data = (u32 *)ucontrol->value.bytes.data; in tegra210_mbdrc_threshold_put()
385 u32 regs = params->soc.base; in tegra210_mbdrc_threshold_put()
386 u32 num_regs = params->soc.num_regs; in tegra210_mbdrc_threshold_put()
390 for (i = 0; i < num_regs; i += 4, regs += cmpnt->val_bytes) { in tegra210_mbdrc_threshold_put()
402 regmap_update_bits_check(ope->mbdrc_regmap, regs, 0xffffffff, in tegra210_mbdrc_threshold_put()
414 struct tegra_soc_bytes *params = (void *)kcontrol->private_value; in tegra210_mbdrc_biquad_coeffs_get()
416 u32 *data = (u32 *)ucontrol->value.bytes.data; in tegra210_mbdrc_biquad_coeffs_get()
418 memset(data, 0, params->soc.num_regs * cmpnt->val_bytes); in tegra210_mbdrc_biquad_coeffs_get()
426 struct tegra_soc_bytes *params = (void *)kcontrol->private_value; in tegra210_mbdrc_biquad_coeffs_put()
429 u32 reg_ctrl = params->soc.base; in tegra210_mbdrc_biquad_coeffs_put()
430 u32 reg_data = reg_ctrl + cmpnt->val_bytes; in tegra210_mbdrc_biquad_coeffs_put()
431 u32 *data = (u32 *)ucontrol->value.bytes.data; in tegra210_mbdrc_biquad_coeffs_put()
433 tegra210_mbdrc_write_ram(ope->mbdrc_regmap, reg_ctrl, reg_data, in tegra210_mbdrc_biquad_coeffs_put()
434 params->shift, data, params->soc.num_regs); in tegra210_mbdrc_biquad_coeffs_put()
442 struct soc_bytes *params = (void *)kcontrol->private_value; in tegra210_mbdrc_param_info()
444 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in tegra210_mbdrc_param_info()
445 uinfo->count = params->num_regs * sizeof(u32); in tegra210_mbdrc_param_info()
454 (struct soc_mixer_control *)kcontrol->private_value; in tegra210_mbdrc_vol_get()
459 regmap_read(ope->mbdrc_regmap, mc->reg, &val); in tegra210_mbdrc_vol_get()
461 ucontrol->value.integer.value[0] = in tegra210_mbdrc_vol_get()
462 ((val >> mc->shift) - TEGRA210_MBDRC_MASTER_VOL_MIN); in tegra210_mbdrc_vol_get()
471 (struct soc_mixer_control *)kcontrol->private_value; in tegra210_mbdrc_vol_put()
474 int val = ucontrol->value.integer.value[0]; in tegra210_mbdrc_vol_put()
479 regmap_update_bits_check(ope->mbdrc_regmap, mc->reg, in tegra210_mbdrc_vol_put()
480 mc->max << mc->shift, val << mc->shift, in tegra210_mbdrc_vol_put()
483 regmap_read(ope->mbdrc_regmap, mc->reg, &val); in tegra210_mbdrc_vol_put()
505 "All-pass-tree", "Flexible"
531 static const DECLARE_TLV_DB_MINMAX(mdbrc_vol_tlv, -25600, 25500);
534 SOC_ENUM_EXT("MBDRC Peak RMS Mode", tegra210_mbdrc_peak_rms_enum,
537 SOC_ENUM_EXT("MBDRC Filter Structure",
541 SOC_ENUM_EXT("MBDRC Frame Size", tegra210_mbdrc_frame_size_enum,
544 SOC_ENUM_EXT("MBDRC Mode", tegra210_mbdrc_mode_enum,
547 SOC_SINGLE_EXT("MBDRC RMS Offset", TEGRA210_MBDRC_CFG,
551 SOC_SINGLE_EXT("MBDRC Shift Control", TEGRA210_MBDRC_CFG,
555 SOC_SINGLE_EXT("MBDRC Fast Attack Factor", TEGRA210_MBDRC_FAST_FACTOR,
559 SOC_SINGLE_EXT("MBDRC Fast Release Factor", TEGRA210_MBDRC_FAST_FACTOR,
563 SOC_SINGLE_RANGE_EXT_TLV("MBDRC Master Volume",
570 TEGRA_SOC_BYTES_EXT("MBDRC IIR Stages", TEGRA210_MBDRC_IIR_CFG,
578 TEGRA_SOC_BYTES_EXT("MBDRC In Attack Time Const", TEGRA210_MBDRC_IN_ATTACK,
586 TEGRA_SOC_BYTES_EXT("MBDRC In Release Time Const", TEGRA210_MBDRC_IN_RELEASE,
594 TEGRA_SOC_BYTES_EXT("MBDRC Fast Attack Time Const", TEGRA210_MBDRC_FAST_ATTACK,
602 TEGRA_SOC_BYTES_EXT("MBDRC In Threshold", TEGRA210_MBDRC_IN_THRESHOLD,
608 TEGRA_SOC_BYTES_EXT("MBDRC Out Threshold", TEGRA210_MBDRC_OUT_THRESHOLD,
614 TEGRA_SOC_BYTES_EXT("MBDRC Ratio", TEGRA210_MBDRC_RATIO_1ST,
621 TEGRA_SOC_BYTES_EXT("MBDRC Makeup Gain", TEGRA210_MBDRC_MAKEUP_GAIN,
629 TEGRA_SOC_BYTES_EXT("MBDRC Init Gain", TEGRA210_MBDRC_INIT_GAIN,
637 TEGRA_SOC_BYTES_EXT("MBDRC Attack Gain", TEGRA210_MBDRC_GAIN_ATTACK,
645 TEGRA_SOC_BYTES_EXT("MBDRC Release Gain", TEGRA210_MBDRC_GAIN_RELEASE,
653 TEGRA_SOC_BYTES_EXT("MBDRC Fast Release Gain",
662 TEGRA_SOC_BYTES_EXT("MBDRC Low Band Biquad Coeffs",
669 TEGRA_SOC_BYTES_EXT("MBDRC Mid Band Biquad Coeffs",
677 TEGRA_SOC_BYTES_EXT("MBDRC High Band Biquad Coeffs",
689 reg -= ((reg - TEGRA210_MBDRC_IIR_CFG) % in tegra210_mbdrc_wr_reg()
709 reg -= ((reg - TEGRA210_MBDRC_IIR_CFG) % in tegra210_mbdrc_rd_reg()
724 reg -= ((reg - TEGRA210_MBDRC_IIR_CFG) % in tegra210_mbdrc_volatile_reg()
742 reg -= ((reg - TEGRA210_MBDRC_IIR_CFG) % in tegra210_mbdrc_precious_reg()
755 .name = "mbdrc",
776 regmap_read(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, &val); in tegra210_mbdrc_hw_params()
785 &conf->band_params[i]; in tegra210_mbdrc_hw_params()
789 tegra210_mbdrc_write_ram(ope->mbdrc_regmap, in tegra210_mbdrc_hw_params()
792 0, (u32 *)¶ms->biquad_params[0], in tegra210_mbdrc_hw_params()
805 pm_runtime_get_sync(cmpnt->dev); in tegra210_mbdrc_component_init()
807 /* Initialize MBDRC registers and AHUB RAM with default params */ in tegra210_mbdrc_component_init()
808 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, in tegra210_mbdrc_component_init()
810 conf->mode << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT); in tegra210_mbdrc_component_init()
812 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, in tegra210_mbdrc_component_init()
814 conf->rms_off << TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT); in tegra210_mbdrc_component_init()
816 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, in tegra210_mbdrc_component_init()
818 conf->peak_rms_mode << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT); in tegra210_mbdrc_component_init()
820 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, in tegra210_mbdrc_component_init()
822 conf->filter_structure << in tegra210_mbdrc_component_init()
825 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, in tegra210_mbdrc_component_init()
827 conf->shift_ctrl << TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT); in tegra210_mbdrc_component_init()
829 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, in tegra210_mbdrc_component_init()
831 __ffs(conf->frame_size) << in tegra210_mbdrc_component_init()
834 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CHANNEL_MASK, in tegra210_mbdrc_component_init()
836 conf->channel_mask << TEGRA210_MBDRC_CHANNEL_MASK_SHIFT); in tegra210_mbdrc_component_init()
838 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_FAST_FACTOR, in tegra210_mbdrc_component_init()
840 conf->fa_factor << TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT); in tegra210_mbdrc_component_init()
842 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_FAST_FACTOR, in tegra210_mbdrc_component_init()
844 conf->fr_factor << TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT); in tegra210_mbdrc_component_init()
848 &conf->band_params[i]; in tegra210_mbdrc_component_init()
851 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
854 params->iir_stages << in tegra210_mbdrc_component_init()
857 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
860 params->in_attack_tc << in tegra210_mbdrc_component_init()
863 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
866 params->in_release_tc << in tegra210_mbdrc_component_init()
869 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
872 params->fast_attack_tc << in tegra210_mbdrc_component_init()
875 val = (((params->in_threshold[0] >> in tegra210_mbdrc_component_init()
878 ((params->in_threshold[1] >> in tegra210_mbdrc_component_init()
881 ((params->in_threshold[2] >> in tegra210_mbdrc_component_init()
884 ((params->in_threshold[3] >> in tegra210_mbdrc_component_init()
888 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
892 val = (((params->out_threshold[0] >> in tegra210_mbdrc_component_init()
895 ((params->out_threshold[1] >> in tegra210_mbdrc_component_init()
898 ((params->out_threshold[2] >> in tegra210_mbdrc_component_init()
901 ((params->out_threshold[3] >> in tegra210_mbdrc_component_init()
905 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
909 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
912 params->ratio[0] << TEGRA210_MBDRC_RATIO_1ST_SHIFT); in tegra210_mbdrc_component_init()
914 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
917 params->ratio[1] << TEGRA210_MBDRC_RATIO_2ND_SHIFT); in tegra210_mbdrc_component_init()
919 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
922 params->ratio[2] << TEGRA210_MBDRC_RATIO_3RD_SHIFT); in tegra210_mbdrc_component_init()
924 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
927 params->ratio[3] << TEGRA210_MBDRC_RATIO_4TH_SHIFT); in tegra210_mbdrc_component_init()
929 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
932 params->ratio[4] << TEGRA210_MBDRC_RATIO_5TH_SHIFT); in tegra210_mbdrc_component_init()
934 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
937 params->makeup_gain << in tegra210_mbdrc_component_init()
940 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
943 params->gain_init << in tegra210_mbdrc_component_init()
946 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
949 params->gain_attack_tc << in tegra210_mbdrc_component_init()
952 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
955 params->gain_release_tc << in tegra210_mbdrc_component_init()
958 regmap_update_bits(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
961 params->fast_release_tc << in tegra210_mbdrc_component_init()
964 tegra210_mbdrc_write_ram(ope->mbdrc_regmap, in tegra210_mbdrc_component_init()
967 (u32 *)¶ms->biquad_params[0], in tegra210_mbdrc_component_init()
971 pm_runtime_put_sync(cmpnt->dev); in tegra210_mbdrc_component_init()
981 struct device *dev = &pdev->dev; in tegra210_mbdrc_regmap_init()
988 child = of_get_child_by_name(dev->of_node, "dynamic-range-compressor"); in tegra210_mbdrc_regmap_init()
990 return -ENODEV; in tegra210_mbdrc_regmap_init()
995 dev_err(dev, "fail to get MBDRC resource\n"); in tegra210_mbdrc_regmap_init()
1004 ope->mbdrc_regmap = devm_regmap_init_mmio(dev, regs, in tegra210_mbdrc_regmap_init()
1006 if (IS_ERR(ope->mbdrc_regmap)) { in tegra210_mbdrc_regmap_init()
1008 return PTR_ERR(ope->mbdrc_regmap); in tegra210_mbdrc_regmap_init()
1011 regcache_cache_only(ope->mbdrc_regmap, true); in tegra210_mbdrc_regmap_init()