Lines Matching +full:0 +full:x8c
13 #define TEGRA210_I2S_RX_ENABLE 0x0
14 #define TEGRA210_I2S_RX_SOFT_RESET 0x4
15 #define TEGRA210_I2S_RX_STATUS 0x0c
16 #define TEGRA210_I2S_RX_INT_STATUS 0x10
17 #define TEGRA210_I2S_RX_INT_MASK 0x14
18 #define TEGRA210_I2S_RX_INT_SET 0x18
19 #define TEGRA210_I2S_RX_INT_CLEAR 0x1c
20 #define TEGRA210_I2S_RX_CIF_CTRL 0x20
21 #define TEGRA210_I2S_RX_CTRL 0x24
22 #define TEGRA210_I2S_RX_SLOT_CTRL 0x28
23 #define TEGRA210_I2S_RX_CLK_TRIM 0x2c
24 #define TEGRA210_I2S_RX_CYA 0x30
25 #define TEGRA210_I2S_RX_CIF_FIFO_STATUS 0x34
26 #define TEGRA210_I2S_TX_ENABLE 0x40
27 #define TEGRA210_I2S_TX_SOFT_RESET 0x44
28 #define TEGRA210_I2S_TX_STATUS 0x4c
29 #define TEGRA210_I2S_TX_INT_STATUS 0x50
30 #define TEGRA210_I2S_TX_INT_MASK 0x54
31 #define TEGRA210_I2S_TX_INT_SET 0x58
32 #define TEGRA210_I2S_TX_INT_CLEAR 0x5c
33 #define TEGRA210_I2S_TX_CIF_CTRL 0x60
34 #define TEGRA210_I2S_TX_CTRL 0x64
35 #define TEGRA210_I2S_TX_SLOT_CTRL 0x68
36 #define TEGRA210_I2S_TX_CLK_TRIM 0x6c
37 #define TEGRA210_I2S_TX_CYA 0x70
38 #define TEGRA210_I2S_TX_CIF_FIFO_STATUS 0x74
39 #define TEGRA210_I2S_ENABLE 0x80
40 #define TEGRA210_I2S_SOFT_RESET 0x84
41 #define TEGRA210_I2S_CG 0x88
42 #define TEGRA210_I2S_STATUS 0x8c
43 #define TEGRA210_I2S_INT_STATUS 0x90
44 #define TEGRA210_I2S_CTRL 0xa0
45 #define TEGRA210_I2S_TIMING 0xa4
46 #define TEGRA210_I2S_SLOT_CTRL 0xa8
47 #define TEGRA210_I2S_CLK_TRIM 0xac
48 #define TEGRA210_I2S_CYA 0xb0
51 #define TEGRA264_I2S_RX_FIFO_WR_ACCESS_MODE 0x30
52 #define TEGRA264_I2S_RX_CYA 0x3c
53 #define TEGRA264_I2S_RX_CIF_FIFO_STATUS 0x40
54 #define TEGRA264_I2S_TX_ENABLE 0x80
55 #define TEGRA264_I2S_TX_SOFT_RESET 0x84
56 #define TEGRA264_I2S_TX_STATUS 0x8c
57 #define TEGRA264_I2S_TX_INT_STATUS 0x90
58 #define TEGRA264_I2S_TX_INT_MASK 0x94
59 #define TEGRA264_I2S_TX_CIF_CTRL 0xa0
60 #define TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE 0xb0
61 #define TEGRA264_I2S_TX_FIFO_RD_DATA 0xb4
62 #define TEGRA264_I2S_TX_FIFO_THRESHOLD 0xb8
63 #define TEGRA264_I2S_TX_CYA 0xbc
64 #define TEGRA264_I2S_TX_CIF_FIFO_STATUS 0xc0
65 #define TEGRA264_I2S_ENABLE 0x100
66 #define TEGRA264_I2S_CG 0x108
67 #define TEGRA264_I2S_STATUS 0x10c
68 #define TEGRA264_I2S_INT_STATUS 0x110
69 #define TEGRA264_I2S_INT_SET 0x114
70 #define TEGRA264_I2S_INT_MASK 0x11c
71 #define TEGRA264_I2S_CTRL 0x12c
72 #define TEGRA264_I2S_TIMING 0x130
73 #define TEGRA264_I2S_CYA 0x13c
74 #define TEGRA264_I2S_PIO_MODE_ENABLE 0x140
75 #define TEGRA264_I2S_PAD_MACRO_STATUS 0x144
79 #define I2S_CTRL_DATA_OFFSET_MASK (0x7ff << I2S_DATA_SHIFT)
81 #define TEGRA264_I2S_CTRL_FSYNC_WIDTH_MASK (0x1ff << TEGRA264_I2S_FSYNC_WIDTH_SHIFT)
83 #define I2S_EN_SHIFT 0
88 #define I2S_CTRL_FSYNC_WIDTH_MASK (0xff << I2S_FSYNC_WIDTH_SHIFT)
90 #define I2S_POS_EDGE 0
97 #define I2S_FMT_LRCK 0
110 #define I2S_CTRL_LRCK_POL_LOW (0 << I2S_CTRL_LRCK_POL_SHIFT)
121 #define I2S_CTRL_BIT_SIZE_MASK 0x7
123 #define I2S_TIMING_CH_BIT_CNT_MASK 0x7ff
124 #define I2S_TIMING_CH_BIT_CNT_SHIFT 0
126 #define I2S_SOFT_RESET_SHIFT 0
133 #define DEFAULT_I2S_SLOT_MASK 0xffff
134 #define TEGRA210_I2S_TX_OFFSET 0
135 #define TEGRA210_I2S_CTRL_OFFSET 0
138 #define TEGRA264_DEFAULT_I2S_SLOT_MASK 0xffffffff
139 #define TEGRA264_I2S_TX_OFFSET 0x40
140 #define TEGRA264_I2S_CTRL_OFFSET 0x8c