Lines Matching +full:i2s +full:- +full:tx +full:- +full:route
1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES.
5 // tegra210_i2s.c - Tegra210 I2S driver
33 * is required to select i2s4b for it to be functional for I2S
51 static void tegra210_i2s_set_slot_ctrl(struct tegra210_i2s *i2s, in tegra210_i2s_set_slot_ctrl() argument
56 regmap_write(i2s->regmap, TEGRA210_I2S_SLOT_CTRL + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_set_slot_ctrl()
57 total_slots - 1); in tegra210_i2s_set_slot_ctrl()
58 regmap_write(i2s->regmap, TEGRA210_I2S_TX_SLOT_CTRL + i2s->soc_data->tx_offset, in tegra210_i2s_set_slot_ctrl()
60 regmap_write(i2s->regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask); in tegra210_i2s_set_slot_ctrl()
66 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_set_clock_rate() local
70 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val); in tegra210_i2s_set_clock_rate()
72 /* No need to set rates if I2S is being operated in slave */ in tegra210_i2s_set_clock_rate()
76 err = clk_set_rate(i2s->clk_i2s, clock_rate); in tegra210_i2s_set_clock_rate()
78 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", in tegra210_i2s_set_clock_rate()
83 if (!IS_ERR(i2s->clk_sync_input)) { in tegra210_i2s_set_clock_rate()
85 * Other I/O modules in AHUB can use i2s bclk as reference in tegra210_i2s_set_clock_rate()
89 err = clk_set_rate(i2s->clk_sync_input, clock_rate); in tegra210_i2s_set_clock_rate()
92 "can't set I2S sync input rate %u, err = %d\n", in tegra210_i2s_set_clock_rate()
104 struct device *dev = compnt->dev; in tegra210_i2s_sw_reset()
105 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_sw_reset() local
117 reset_reg = TEGRA210_I2S_TX_SOFT_RESET + i2s->soc_data->tx_offset; in tegra210_i2s_sw_reset()
118 cif_reg = TEGRA210_I2S_TX_CIF_CTRL + i2s->soc_data->tx_offset; in tegra210_i2s_sw_reset()
119 stream_reg = TEGRA210_I2S_TX_CTRL + i2s->soc_data->tx_offset; in tegra210_i2s_sw_reset()
122 /* Store CIF and I2S control values */ in tegra210_i2s_sw_reset()
123 regmap_read(i2s->regmap, cif_reg, &cif_ctrl); in tegra210_i2s_sw_reset()
124 regmap_read(i2s->regmap, stream_reg, &stream_ctrl); in tegra210_i2s_sw_reset()
125 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &i2s_ctrl); in tegra210_i2s_sw_reset()
128 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en); in tegra210_i2s_sw_reset()
130 err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val, in tegra210_i2s_sw_reset()
134 dev_err(dev, "timeout: failed to reset I2S for %s\n", in tegra210_i2s_sw_reset()
139 /* Restore CIF and I2S control values */ in tegra210_i2s_sw_reset()
140 regmap_write(i2s->regmap, cif_reg, cif_ctrl); in tegra210_i2s_sw_reset()
141 regmap_write(i2s->regmap, stream_reg, stream_ctrl); in tegra210_i2s_sw_reset()
142 regmap_write(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, i2s_ctrl); in tegra210_i2s_sw_reset()
150 struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm); in tegra210_i2s_init()
151 struct device *dev = compnt->dev; in tegra210_i2s_init()
152 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_init() local
157 if (w->reg == TEGRA210_I2S_RX_ENABLE) { in tegra210_i2s_init()
160 } else if (w->reg == (TEGRA210_I2S_TX_ENABLE + i2s->soc_data->tx_offset)) { in tegra210_i2s_init()
162 status_reg = TEGRA210_I2S_TX_STATUS + i2s->soc_data->tx_offset; in tegra210_i2s_init()
164 return -EINVAL; in tegra210_i2s_init()
167 /* Ensure I2S is in disabled state before new session */ in tegra210_i2s_init()
168 err = regmap_read_poll_timeout(i2s->regmap, status_reg, val, in tegra210_i2s_init()
172 dev_err(dev, "timeout: previous I2S %s is still active\n", in tegra210_i2s_init()
182 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_runtime_suspend() local
184 regcache_cache_only(i2s->regmap, true); in tegra210_i2s_runtime_suspend()
185 regcache_mark_dirty(i2s->regmap); in tegra210_i2s_runtime_suspend()
187 clk_disable_unprepare(i2s->clk_i2s); in tegra210_i2s_runtime_suspend()
194 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_runtime_resume() local
197 err = clk_prepare_enable(i2s->clk_i2s); in tegra210_i2s_runtime_resume()
199 dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err); in tegra210_i2s_runtime_resume()
203 regcache_cache_only(i2s->regmap, false); in tegra210_i2s_runtime_resume()
204 regcache_sync(i2s->regmap); in tegra210_i2s_runtime_resume()
209 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s, in tegra210_i2s_set_data_offset() argument
213 regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL + i2s->soc_data->tx_offset, in tegra210_i2s_set_data_offset()
218 regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL, in tegra210_i2s_set_data_offset()
226 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra210_i2s_set_fmt() local
238 return -EINVAL; in tegra210_i2s_set_fmt()
246 tegra210_i2s_set_data_offset(i2s, 1); in tegra210_i2s_set_fmt()
251 tegra210_i2s_set_data_offset(i2s, 0); in tegra210_i2s_set_fmt()
253 /* I2S mode has data offset of 1 */ in tegra210_i2s_set_fmt()
257 tegra210_i2s_set_data_offset(i2s, 1); in tegra210_i2s_set_fmt()
270 tegra210_i2s_set_data_offset(i2s, 0); in tegra210_i2s_set_fmt()
273 return -EINVAL; in tegra210_i2s_set_fmt()
293 return -EINVAL; in tegra210_i2s_set_fmt()
296 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_set_fmt()
299 i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; in tegra210_i2s_set_fmt()
308 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra210_i2s_set_tdm_slot() local
310 /* Copy the required tx and rx mask */ in tegra210_i2s_set_tdm_slot()
311 i2s->tx_mask = (tx_mask > i2s->soc_data->slot_mask) ? in tegra210_i2s_set_tdm_slot()
312 i2s->soc_data->slot_mask : tx_mask; in tegra210_i2s_set_tdm_slot()
313 i2s->rx_mask = (rx_mask > i2s->soc_data->slot_mask) ? in tegra210_i2s_set_tdm_slot()
314 i2s->soc_data->slot_mask : rx_mask; in tegra210_i2s_set_tdm_slot()
323 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_get_loopback() local
325 ucontrol->value.integer.value[0] = i2s->loopback; in tegra210_i2s_get_loopback()
334 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_put_loopback() local
335 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_put_loopback()
337 if (value == i2s->loopback) in tegra210_i2s_put_loopback()
340 i2s->loopback = value; in tegra210_i2s_put_loopback()
342 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_put_loopback()
343 I2S_CTRL_LPBK_MASK, i2s->loopback << I2S_CTRL_LPBK_SHIFT); in tegra210_i2s_put_loopback()
352 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_get_fsync_width() local
354 ucontrol->value.integer.value[0] = i2s->fsync_width; in tegra210_i2s_get_fsync_width()
363 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_put_fsync_width() local
364 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_put_fsync_width()
366 if (value == i2s->fsync_width) in tegra210_i2s_put_fsync_width()
369 i2s->fsync_width = value; in tegra210_i2s_put_fsync_width()
379 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_put_fsync_width()
380 i2s->soc_data->fsync_width_mask, in tegra210_i2s_put_fsync_width()
381 i2s->fsync_width << i2s->soc_data->fsync_width_shift); in tegra210_i2s_put_fsync_width()
390 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_cget_stereo_to_mono() local
392 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH]; in tegra210_i2s_cget_stereo_to_mono()
401 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_cput_stereo_to_mono() local
402 unsigned int value = ucontrol->value.enumerated.item[0]; in tegra210_i2s_cput_stereo_to_mono()
404 if (value == i2s->stereo_to_mono[I2S_TX_PATH]) in tegra210_i2s_cput_stereo_to_mono()
407 i2s->stereo_to_mono[I2S_TX_PATH] = value; in tegra210_i2s_cput_stereo_to_mono()
416 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_cget_mono_to_stereo() local
418 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH]; in tegra210_i2s_cget_mono_to_stereo()
427 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_cput_mono_to_stereo() local
428 unsigned int value = ucontrol->value.enumerated.item[0]; in tegra210_i2s_cput_mono_to_stereo()
430 if (value == i2s->mono_to_stereo[I2S_TX_PATH]) in tegra210_i2s_cput_mono_to_stereo()
433 i2s->mono_to_stereo[I2S_TX_PATH] = value; in tegra210_i2s_cput_mono_to_stereo()
442 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_pget_stereo_to_mono() local
444 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH]; in tegra210_i2s_pget_stereo_to_mono()
453 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_pput_stereo_to_mono() local
454 unsigned int value = ucontrol->value.enumerated.item[0]; in tegra210_i2s_pput_stereo_to_mono()
456 if (value == i2s->stereo_to_mono[I2S_RX_PATH]) in tegra210_i2s_pput_stereo_to_mono()
459 i2s->stereo_to_mono[I2S_RX_PATH] = value; in tegra210_i2s_pput_stereo_to_mono()
468 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_pget_mono_to_stereo() local
470 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH]; in tegra210_i2s_pget_mono_to_stereo()
479 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_pput_mono_to_stereo() local
480 unsigned int value = ucontrol->value.enumerated.item[0]; in tegra210_i2s_pput_mono_to_stereo()
482 if (value == i2s->mono_to_stereo[I2S_RX_PATH]) in tegra210_i2s_pput_mono_to_stereo()
485 i2s->mono_to_stereo[I2S_RX_PATH] = value; in tegra210_i2s_pput_mono_to_stereo()
494 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_pget_fifo_th() local
496 ucontrol->value.integer.value[0] = i2s->rx_fifo_th; in tegra210_i2s_pget_fifo_th()
505 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_pput_fifo_th() local
506 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_pput_fifo_th()
508 if (value == i2s->rx_fifo_th) in tegra210_i2s_pput_fifo_th()
511 i2s->rx_fifo_th = value; in tegra210_i2s_pput_fifo_th()
520 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_get_bclk_ratio() local
522 ucontrol->value.integer.value[0] = i2s->bclk_ratio; in tegra210_i2s_get_bclk_ratio()
531 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_put_bclk_ratio() local
532 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_put_bclk_ratio()
534 if (value == i2s->bclk_ratio) in tegra210_i2s_put_bclk_ratio()
537 i2s->bclk_ratio = value; in tegra210_i2s_put_bclk_ratio()
545 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra210_i2s_set_dai_bclk_ratio() local
547 i2s->bclk_ratio = ratio; in tegra210_i2s_set_dai_bclk_ratio()
557 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_set_timing_params() local
561 if (i2s->bclk_ratio) in tegra210_i2s_set_timing_params()
562 num_bclk *= i2s->bclk_ratio; in tegra210_i2s_set_timing_params()
564 if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) in tegra210_i2s_set_timing_params()
565 tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size); in tegra210_i2s_set_timing_params()
567 /* I2S bit clock rate */ in tegra210_i2s_set_timing_params()
572 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", in tegra210_i2s_set_timing_params()
577 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val); in tegra210_i2s_set_timing_params()
588 bit_count = (bclk_rate / (srate * 2)) - 1; in tegra210_i2s_set_timing_params()
591 bit_count = (bclk_rate / srate) - 1; in tegra210_i2s_set_timing_params()
593 tegra210_i2s_set_slot_ctrl(i2s, channels, in tegra210_i2s_set_timing_params()
594 i2s->tx_mask, i2s->rx_mask); in tegra210_i2s_set_timing_params()
597 dev_err(dev, "invalid I2S frame format\n"); in tegra210_i2s_set_timing_params()
598 return -EINVAL; in tegra210_i2s_set_timing_params()
602 dev_err(dev, "invalid I2S channel bit count %u\n", bit_count); in tegra210_i2s_set_timing_params()
603 return -EINVAL; in tegra210_i2s_set_timing_params()
606 regmap_write(i2s->regmap, TEGRA210_I2S_TIMING + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_set_timing_params()
616 struct device *dev = dai->dev; in tegra210_i2s_hw_params()
617 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra210_i2s_hw_params() local
626 dev_err(dev, "invalid I2S %d channel configuration\n", in tegra210_i2s_hw_params()
628 return -EINVAL; in tegra210_i2s_hw_params()
633 if (i2s->client_channels) in tegra210_i2s_hw_params()
634 cif_conf.client_ch = i2s->client_channels; in tegra210_i2s_hw_params()
650 return -EOPNOTSUPP; in tegra210_i2s_hw_params()
654 if (i2s->client_sample_format >= 0) in tegra210_i2s_hw_params()
655 sample_format = (snd_pcm_format_t)i2s->client_sample_format; in tegra210_i2s_hw_params()
658 * Format of the I2S for sending/receiving the audio in tegra210_i2s_hw_params()
684 return -EOPNOTSUPP; in tegra210_i2s_hw_params()
688 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_hw_params()
693 /* For playback I2S RX-CIF and for capture TX-CIF is used */ in tegra210_i2s_hw_params()
694 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra210_i2s_hw_params()
699 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in tegra210_i2s_hw_params()
703 max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1; in tegra210_i2s_hw_params()
705 if (i2s->rx_fifo_th > max_th) in tegra210_i2s_hw_params()
706 i2s->rx_fifo_th = max_th; in tegra210_i2s_hw_params()
708 cif_conf.threshold = i2s->rx_fifo_th; in tegra210_i2s_hw_params()
712 reg = TEGRA210_I2S_TX_CIF_CTRL + i2s->soc_data->tx_offset; in tegra210_i2s_hw_params()
715 cif_conf.mono_conv = i2s->mono_to_stereo[path]; in tegra210_i2s_hw_params()
716 cif_conf.stereo_conv = i2s->stereo_to_mono[path]; in tegra210_i2s_hw_params()
718 if (i2s->soc_data->max_ch == TEGRA264_I2S_MAX_CHANNEL) in tegra210_i2s_hw_params()
719 tegra264_set_cif(i2s->regmap, reg, &cif_conf); in tegra210_i2s_hw_params()
721 tegra_set_cif(i2s->regmap, reg, &cif_conf); in tegra210_i2s_hw_params()
736 .name = "I2S-CIF",
738 .stream_name = "CIF-Playback",
748 .stream_name = "CIF-Capture",
759 .name = "I2S-DAP",
761 .stream_name = "DAP-Playback",
771 .stream_name = "DAP-Capture",
819 SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1,
829 SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, tx_enable_reg, \
843 /* Playback route from XBAR */
844 { "XBAR-Playback", NULL, "XBAR-TX" },
845 { "CIF-Playback", NULL, "XBAR-Playback" },
846 { "RX", NULL, "CIF-Playback" },
847 { "DAP-Playback", NULL, "RX" },
848 { "SPK", NULL, "DAP-Playback" },
849 /* Capture route to XBAR */
850 { "XBAR-RX", NULL, "XBAR-Capture" },
851 { "XBAR-Capture", NULL, "CIF-Capture" },
852 { "CIF-Capture", NULL, "TX" },
853 { "TX", NULL, "DAP-Capture" },
854 { "DAP-Capture", NULL, "MIC" },
1008 * CIF Port of DT I2S node which can help to perform this conversion.
1011 * -----> ADMAIF -----------> CIF -------------> I2S ---->
1015 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_parse_client_convert() local
1020 ports = of_get_child_by_name(dev->of_node, "ports"); in tegra210_parse_client_convert()
1022 ep = of_graph_get_endpoint_by_regs(ports, cif_port, -1); in tegra210_parse_client_convert()
1031 i2s->client_channels = data.convert_channels; in tegra210_parse_client_convert()
1034 i2s->client_sample_format = simple_util_get_sample_fmt(&data); in tegra210_parse_client_convert()
1052 struct device *dev = &pdev->dev; in tegra210_i2s_probe()
1053 struct tegra210_i2s *i2s; in tegra210_i2s_probe() local
1057 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); in tegra210_i2s_probe()
1058 if (!i2s) in tegra210_i2s_probe()
1059 return -ENOMEM; in tegra210_i2s_probe()
1061 i2s->soc_data = of_device_get_match_data(&pdev->dev); in tegra210_i2s_probe()
1062 i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD; in tegra210_i2s_probe()
1063 i2s->tx_mask = i2s->soc_data->slot_mask; in tegra210_i2s_probe()
1064 i2s->rx_mask = i2s->soc_data->slot_mask; in tegra210_i2s_probe()
1065 i2s->loopback = false; in tegra210_i2s_probe()
1066 i2s->client_sample_format = -EINVAL; in tegra210_i2s_probe()
1068 dev_set_drvdata(dev, i2s); in tegra210_i2s_probe()
1070 i2s->clk_i2s = devm_clk_get(dev, "i2s"); in tegra210_i2s_probe()
1071 if (IS_ERR(i2s->clk_i2s)) { in tegra210_i2s_probe()
1072 dev_err(dev, "can't retrieve I2S bit clock\n"); in tegra210_i2s_probe()
1073 return PTR_ERR(i2s->clk_i2s); in tegra210_i2s_probe()
1078 * requires input clock from current I2S instance, which is in tegra210_i2s_probe()
1081 i2s->clk_sync_input = devm_clk_get(dev, "sync_input"); in tegra210_i2s_probe()
1082 if (IS_ERR(i2s->clk_sync_input)) in tegra210_i2s_probe()
1083 dev_dbg(dev, "can't retrieve I2S sync input clock\n"); in tegra210_i2s_probe()
1089 i2s->regmap = devm_regmap_init_mmio(dev, regs, in tegra210_i2s_probe()
1090 i2s->soc_data->regmap_conf); in tegra210_i2s_probe()
1091 if (IS_ERR(i2s->regmap)) { in tegra210_i2s_probe()
1093 return PTR_ERR(i2s->regmap); in tegra210_i2s_probe()
1098 regcache_cache_only(i2s->regmap, true); in tegra210_i2s_probe()
1102 tegra210_i2s_dais[id].playback.channels_max = i2s->soc_data->max_ch; in tegra210_i2s_probe()
1103 tegra210_i2s_dais[id].capture.channels_max = i2s->soc_data->max_ch; in tegra210_i2s_probe()
1106 err = devm_snd_soc_register_component(dev, i2s->soc_data->i2s_cmpnt, in tegra210_i2s_probe()
1110 dev_err(dev, "can't register I2S component, err: %d\n", err); in tegra210_i2s_probe()
1121 pm_runtime_disable(&pdev->dev); in tegra210_i2s_remove()
1153 { .compatible = "nvidia,tegra210-i2s", .data = &soc_data_tegra210 },
1154 { .compatible = "nvidia,tegra264-i2s", .data = &soc_data_tegra264 },
1161 .name = "tegra210-i2s",
1171 MODULE_DESCRIPTION("Tegra210 ASoC I2S driver");