Lines Matching +full:capture +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES.
5 // tegra210_i2s.c - Tegra210 I2S driver
44 regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1); in tegra210_i2s_set_slot_ctrl()
56 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val); in tegra210_i2s_set_clock_rate()
62 err = clk_set_rate(i2s->clk_i2s, clock_rate); in tegra210_i2s_set_clock_rate()
69 if (!IS_ERR(i2s->clk_sync_input)) { in tegra210_i2s_set_clock_rate()
75 err = clk_set_rate(i2s->clk_sync_input, clock_rate); in tegra210_i2s_set_clock_rate()
90 struct device *dev = compnt->dev; in tegra210_i2s_sw_reset()
109 regmap_read(i2s->regmap, cif_reg, &cif_ctrl); in tegra210_i2s_sw_reset()
110 regmap_read(i2s->regmap, stream_reg, &stream_ctrl); in tegra210_i2s_sw_reset()
111 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &i2s_ctrl); in tegra210_i2s_sw_reset()
114 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en); in tegra210_i2s_sw_reset()
116 err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val, in tegra210_i2s_sw_reset()
126 regmap_write(i2s->regmap, cif_reg, cif_ctrl); in tegra210_i2s_sw_reset()
127 regmap_write(i2s->regmap, stream_reg, stream_ctrl); in tegra210_i2s_sw_reset()
128 regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, i2s_ctrl); in tegra210_i2s_sw_reset()
136 struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm); in tegra210_i2s_init()
137 struct device *dev = compnt->dev; in tegra210_i2s_init()
143 switch (w->reg) { in tegra210_i2s_init()
153 return -EINVAL; in tegra210_i2s_init()
157 err = regmap_read_poll_timeout(i2s->regmap, status_reg, val, in tegra210_i2s_init()
173 regcache_cache_only(i2s->regmap, true); in tegra210_i2s_runtime_suspend()
174 regcache_mark_dirty(i2s->regmap); in tegra210_i2s_runtime_suspend()
176 clk_disable_unprepare(i2s->clk_i2s); in tegra210_i2s_runtime_suspend()
186 err = clk_prepare_enable(i2s->clk_i2s); in tegra210_i2s_runtime_resume()
192 regcache_cache_only(i2s->regmap, false); in tegra210_i2s_runtime_resume()
193 regcache_sync(i2s->regmap); in tegra210_i2s_runtime_resume()
201 /* Capture path */ in tegra210_i2s_set_data_offset()
202 regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL, in tegra210_i2s_set_data_offset()
207 regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL, in tegra210_i2s_set_data_offset()
227 return -EINVAL; in tegra210_i2s_set_fmt()
262 return -EINVAL; in tegra210_i2s_set_fmt()
282 return -EINVAL; in tegra210_i2s_set_fmt()
285 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val); in tegra210_i2s_set_fmt()
287 i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; in tegra210_i2s_set_fmt()
299 i2s->tx_mask = (tx_mask > DEFAULT_I2S_SLOT_MASK) ? in tegra210_i2s_set_tdm_slot()
301 i2s->rx_mask = (rx_mask > DEFAULT_I2S_SLOT_MASK) ? in tegra210_i2s_set_tdm_slot()
313 ucontrol->value.integer.value[0] = i2s->loopback; in tegra210_i2s_get_loopback()
323 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_put_loopback()
325 if (value == i2s->loopback) in tegra210_i2s_put_loopback()
328 i2s->loopback = value; in tegra210_i2s_put_loopback()
330 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, I2S_CTRL_LPBK_MASK, in tegra210_i2s_put_loopback()
331 i2s->loopback << I2S_CTRL_LPBK_SHIFT); in tegra210_i2s_put_loopback()
342 ucontrol->value.integer.value[0] = i2s->fsync_width; in tegra210_i2s_get_fsync_width()
352 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_put_fsync_width()
354 if (value == i2s->fsync_width) in tegra210_i2s_put_fsync_width()
357 i2s->fsync_width = value; in tegra210_i2s_put_fsync_width()
367 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, in tegra210_i2s_put_fsync_width()
369 i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT); in tegra210_i2s_put_fsync_width()
380 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH]; in tegra210_i2s_cget_stereo_to_mono()
390 unsigned int value = ucontrol->value.enumerated.item[0]; in tegra210_i2s_cput_stereo_to_mono()
392 if (value == i2s->stereo_to_mono[I2S_TX_PATH]) in tegra210_i2s_cput_stereo_to_mono()
395 i2s->stereo_to_mono[I2S_TX_PATH] = value; in tegra210_i2s_cput_stereo_to_mono()
406 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH]; in tegra210_i2s_cget_mono_to_stereo()
416 unsigned int value = ucontrol->value.enumerated.item[0]; in tegra210_i2s_cput_mono_to_stereo()
418 if (value == i2s->mono_to_stereo[I2S_TX_PATH]) in tegra210_i2s_cput_mono_to_stereo()
421 i2s->mono_to_stereo[I2S_TX_PATH] = value; in tegra210_i2s_cput_mono_to_stereo()
432 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH]; in tegra210_i2s_pget_stereo_to_mono()
442 unsigned int value = ucontrol->value.enumerated.item[0]; in tegra210_i2s_pput_stereo_to_mono()
444 if (value == i2s->stereo_to_mono[I2S_RX_PATH]) in tegra210_i2s_pput_stereo_to_mono()
447 i2s->stereo_to_mono[I2S_RX_PATH] = value; in tegra210_i2s_pput_stereo_to_mono()
458 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH]; in tegra210_i2s_pget_mono_to_stereo()
468 unsigned int value = ucontrol->value.enumerated.item[0]; in tegra210_i2s_pput_mono_to_stereo()
470 if (value == i2s->mono_to_stereo[I2S_RX_PATH]) in tegra210_i2s_pput_mono_to_stereo()
473 i2s->mono_to_stereo[I2S_RX_PATH] = value; in tegra210_i2s_pput_mono_to_stereo()
484 ucontrol->value.integer.value[0] = i2s->rx_fifo_th; in tegra210_i2s_pget_fifo_th()
494 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_pput_fifo_th()
496 if (value == i2s->rx_fifo_th) in tegra210_i2s_pput_fifo_th()
499 i2s->rx_fifo_th = value; in tegra210_i2s_pput_fifo_th()
510 ucontrol->value.integer.value[0] = i2s->bclk_ratio; in tegra210_i2s_get_bclk_ratio()
520 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_put_bclk_ratio()
522 if (value == i2s->bclk_ratio) in tegra210_i2s_put_bclk_ratio()
525 i2s->bclk_ratio = value; in tegra210_i2s_put_bclk_ratio()
535 i2s->bclk_ratio = ratio; in tegra210_i2s_set_dai_bclk_ratio()
543 unsigned int channels) in tegra210_i2s_set_timing_params() argument
549 if (i2s->bclk_ratio) in tegra210_i2s_set_timing_params()
550 num_bclk *= i2s->bclk_ratio; in tegra210_i2s_set_timing_params()
552 if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) in tegra210_i2s_set_timing_params()
553 tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size); in tegra210_i2s_set_timing_params()
556 bclk_rate = srate * channels * num_bclk; in tegra210_i2s_set_timing_params()
565 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val); in tegra210_i2s_set_timing_params()
570 * the number of bit clocks in both left and right channels for DSP in tegra210_i2s_set_timing_params()
576 bit_count = (bclk_rate / (srate * 2)) - 1; in tegra210_i2s_set_timing_params()
579 bit_count = (bclk_rate / srate) - 1; in tegra210_i2s_set_timing_params()
581 tegra210_i2s_set_slot_ctrl(i2s->regmap, channels, in tegra210_i2s_set_timing_params()
582 i2s->tx_mask, i2s->rx_mask); in tegra210_i2s_set_timing_params()
586 return -EINVAL; in tegra210_i2s_set_timing_params()
591 return -EINVAL; in tegra210_i2s_set_timing_params()
594 regmap_write(i2s->regmap, TEGRA210_I2S_TIMING, in tegra210_i2s_set_timing_params()
604 struct device *dev = dai->dev; in tegra210_i2s_hw_params()
606 unsigned int sample_size, channels, srate, val, reg, path; in tegra210_i2s_hw_params() local
612 channels = params_channels(params); in tegra210_i2s_hw_params()
613 if (channels < 1) { in tegra210_i2s_hw_params()
615 channels); in tegra210_i2s_hw_params()
616 return -EINVAL; in tegra210_i2s_hw_params()
619 cif_conf.audio_ch = channels; in tegra210_i2s_hw_params()
620 cif_conf.client_ch = channels; in tegra210_i2s_hw_params()
621 if (i2s->client_channels) in tegra210_i2s_hw_params()
622 cif_conf.client_ch = i2s->client_channels; in tegra210_i2s_hw_params()
638 return -EOPNOTSUPP; in tegra210_i2s_hw_params()
642 if (i2s->client_sample_format >= 0) in tegra210_i2s_hw_params()
643 sample_format = (snd_pcm_format_t)i2s->client_sample_format; in tegra210_i2s_hw_params()
672 return -EOPNOTSUPP; in tegra210_i2s_hw_params()
676 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, in tegra210_i2s_hw_params()
681 /* For playback I2S RX-CIF and for capture TX-CIF is used */ in tegra210_i2s_hw_params()
682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra210_i2s_hw_params()
687 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in tegra210_i2s_hw_params()
691 max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1; in tegra210_i2s_hw_params()
693 if (i2s->rx_fifo_th > max_th) in tegra210_i2s_hw_params()
694 i2s->rx_fifo_th = max_th; in tegra210_i2s_hw_params()
696 cif_conf.threshold = i2s->rx_fifo_th; in tegra210_i2s_hw_params()
703 cif_conf.mono_conv = i2s->mono_to_stereo[path]; in tegra210_i2s_hw_params()
704 cif_conf.stereo_conv = i2s->stereo_to_mono[path]; in tegra210_i2s_hw_params()
706 tegra_set_cif(i2s->regmap, reg, &cif_conf); in tegra210_i2s_hw_params()
721 .name = "I2S-CIF",
723 .stream_name = "CIF-Playback",
732 .capture = {
733 .stream_name = "CIF-Capture",
744 .name = "I2S-DAP",
746 .stream_name = "DAP-Playback",
755 .capture = {
756 .stream_name = "DAP-Capture",
792 SOC_ENUM_EXT("Capture Stereo To Mono", tegra210_i2s_stereo_conv_enum,
795 SOC_ENUM_EXT("Capture Mono To Stereo", tegra210_i2s_mono_conv_enum,
804 SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1,
822 { "XBAR-Playback", NULL, "XBAR-TX" },
823 { "CIF-Playback", NULL, "XBAR-Playback" },
824 { "RX", NULL, "CIF-Playback" },
825 { "DAP-Playback", NULL, "RX" },
826 { "SPK", NULL, "DAP-Playback" },
827 /* Capture route to XBAR */
828 { "XBAR-RX", NULL, "XBAR-Capture" },
829 { "XBAR-Capture", NULL, "CIF-Capture" },
830 { "CIF-Capture", NULL, "TX" },
831 { "TX", NULL, "DAP-Capture" },
832 { "DAP-Capture", NULL, "MIC" },
919 * -----> ADMAIF -----------> CIF -------------> I2S ---->
928 ports = of_get_child_by_name(dev->of_node, "ports"); in tegra210_parse_client_convert()
930 ep = of_graph_get_endpoint_by_regs(ports, cif_port, -1); in tegra210_parse_client_convert()
939 i2s->client_channels = data.convert_channels; in tegra210_parse_client_convert()
942 i2s->client_sample_format = simple_util_get_sample_fmt(&data); in tegra210_parse_client_convert()
947 struct device *dev = &pdev->dev; in tegra210_i2s_probe()
954 return -ENOMEM; in tegra210_i2s_probe()
956 i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD; in tegra210_i2s_probe()
957 i2s->tx_mask = DEFAULT_I2S_SLOT_MASK; in tegra210_i2s_probe()
958 i2s->rx_mask = DEFAULT_I2S_SLOT_MASK; in tegra210_i2s_probe()
959 i2s->loopback = false; in tegra210_i2s_probe()
960 i2s->client_sample_format = -EINVAL; in tegra210_i2s_probe()
964 i2s->clk_i2s = devm_clk_get(dev, "i2s"); in tegra210_i2s_probe()
965 if (IS_ERR(i2s->clk_i2s)) { in tegra210_i2s_probe()
967 return PTR_ERR(i2s->clk_i2s); in tegra210_i2s_probe()
975 i2s->clk_sync_input = devm_clk_get(dev, "sync_input"); in tegra210_i2s_probe()
976 if (IS_ERR(i2s->clk_sync_input)) in tegra210_i2s_probe()
983 i2s->regmap = devm_regmap_init_mmio(dev, regs, in tegra210_i2s_probe()
985 if (IS_ERR(i2s->regmap)) { in tegra210_i2s_probe()
987 return PTR_ERR(i2s->regmap); in tegra210_i2s_probe()
992 regcache_cache_only(i2s->regmap, true); in tegra210_i2s_probe()
1009 pm_runtime_disable(&pdev->dev); in tegra210_i2s_remove()
1020 { .compatible = "nvidia,tegra210-i2s" },
1027 .name = "tegra210-i2s",