Lines Matching +full:rx +full:- +full:inactive
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
6 * Copyright (C) 2011 - NVIDIA, Inc.
9 * Copyright (c) 2008-2009, NVIDIA Corporation
45 /* SPDIF receiver(RX) enable */
75 /* Interrupt when RX user FIFO attention level is reached */
81 /* Interrupt when RX data FIFO attention level is reached */
124 * Receiver(RX) shifter is busy receiving data.
129 * (b) the SPDIF data stream becomes inactive.
163 /* RX FIFO Overrun error status */
169 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
173 * RX channel block data receive status:
179 /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
183 * RX User FIFO Status:
195 * RX Data FIFO Status:
210 * bi-phase period.
215 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
219 * Manual data strobe time within the bi-phase clock period (in terms of
220 * the number of over-sampling clocks).
226 * Manual SPDIFIN bi-phase clock period (in terms of the number of
227 * over-sampling clocks).
234 /* Clear Receiver User FIFO (RX USR.FIFO) */
255 /* Number of RX USR.FIFO levels with valid data. */
279 /* Clear Receiver Data FIFO (RX DATA.FIFO) */
300 /* Number of RX DATA.FIFO levels with valid data. */
328 * 16-bit (BIT_MODE=00, PACK=0)
329 * 20-bit (BIT_MODE=01, PACK=0)
330 * 24-bit (BIT_MODE=10, PACK=0)
332 * 16-bit packed (BIT_MODE=00, PACK=1)
368 * 16-bit (BIT_MODE=00, PACK=0)
369 * 20-bit (BIT_MODE=01, PACK=0)
370 * 24-bit (BIT_MODE=10, PACK=0)
372 * 16-bit packed (BIT_MODE=00, PACK=1)
374 * Bits 31:24 are common to all modes except 16-bit packed
417 * The 6-word receive channel data page buffer holds a block (192 frames) of
430 * The 6-word transmit channel data page buffer holds a block (192 frames) of
438 * This 4-word deep FIFO receives user FIFO field information. The order of
445 * This 4-word deep FIFO transmits user FIFO field information. The order of