Lines Matching +full:i2s +full:- +full:regs
1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_spdif.c - Tegra20 SPDIF driver
6 * Copyright (C) 2011-2012 - NVIDIA, Inc.
32 regcache_cache_only(spdif->regmap, true);
34 clk_disable_unprepare(spdif->clk_spdif_out);
44 ret = reset_control_assert(spdif->reset);
48 ret = clk_prepare_enable(spdif->clk_spdif_out);
56 ret = reset_control_deassert(spdif->reset);
60 regcache_cache_only(spdif->regmap, false);
61 regcache_mark_dirty(spdif->regmap);
63 ret = regcache_sync(spdif->regmap);
70 clk_disable_unprepare(spdif->clk_spdif_out);
79 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
92 return -EINVAL;
95 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
101 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_DATA_FIFO_CSR,
128 return -EINVAL;
131 ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
133 dev_err(dai->dev, "Can't set SPDIF clock rate: %d\n", ret);
137 rate = clk_get_rate(spdif->clk_spdif_out);
139 dev_warn_once(dai->dev,
148 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
155 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
162 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
176 return -EINVAL;
185 struct snd_interval *r = hw_param_interval(params, rule->var);
186 struct snd_soc_dai *dai = rule->private;
187 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
188 struct clk *parent = clk_get_parent(spdif->clk_spdif_out);
194 dev_err(dai->dev, "Can't get parent clock rate\n");
195 return -EINVAL;
208 valid_rates = BIT(ARRAY_SIZE(rates)) - 1;
216 if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate"))
220 * SPDIF and I2S share audio PLL. HDMI takes audio packets from SPDIF
223 * PLL rate is controlled by I2S side. Filter out audio rates that
225 * and I2S work simultaneously, assuming that PLL rate won't be
228 return snd_pcm_hw_rule_add(substream->runtime, 0,
231 SNDRV_PCM_HW_PARAM_RATE, -1);
236 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
238 snd_soc_dai_init_dma_data(dai, &spdif->playback_dma_data, NULL);
251 .name = "tegra20-spdif",
264 .name = "tegra20-spdif",
347 void __iomem *regs;
350 spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
353 return -ENOMEM;
355 dev_set_drvdata(&pdev->dev, spdif);
357 spdif->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
358 if (IS_ERR(spdif->reset)) {
359 dev_err(&pdev->dev, "Can't retrieve spdif reset\n");
360 return PTR_ERR(spdif->reset);
363 spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "out");
364 if (IS_ERR(spdif->clk_spdif_out)) {
365 dev_err(&pdev->dev, "Could not retrieve spdif clock\n");
366 return PTR_ERR(spdif->clk_spdif_out);
369 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
370 if (IS_ERR(regs))
371 return PTR_ERR(regs);
373 spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
375 if (IS_ERR(spdif->regmap)) {
376 dev_err(&pdev->dev, "regmap init failed\n");
377 return PTR_ERR(spdif->regmap);
380 spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
381 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
382 spdif->playback_dma_data.maxburst = 4;
384 ret = devm_pm_runtime_enable(&pdev->dev);
388 ret = devm_snd_soc_register_component(&pdev->dev,
392 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
396 ret = devm_tegra_pcm_platform_register(&pdev->dev);
398 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
412 { .compatible = "nvidia,tegra20-spdif", },
419 .name = "tegra20-spdif",