Lines Matching +full:int +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION. All rights reserved.
4 // tegra186_asrc.c - Tegra186 ASRC driver
70 unsigned int id) in tegra186_asrc_lock_stream()
72 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
78 static int tegra186_asrc_runtime_suspend(struct device *dev) in tegra186_asrc_runtime_suspend()
82 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
83 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
88 static int tegra186_asrc_runtime_resume(struct device *dev) in tegra186_asrc_runtime_resume()
91 int id; in tegra186_asrc_runtime_resume()
93 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
100 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
101 asrc->soc_data->aram_start_addr); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
105 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
108 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
112 regmap_write(asrc->regmap, in tegra186_asrc_runtime_resume()
115 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
117 regmap_write(asrc->regmap, in tegra186_asrc_runtime_resume()
120 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
128 static int tegra186_asrc_set_audio_cif(struct tegra186_asrc *asrc, in tegra186_asrc_set_audio_cif()
130 unsigned int reg) in tegra186_asrc_set_audio_cif()
132 int channels, audio_bits; in tegra186_asrc_set_audio_cif()
148 return -EINVAL; in tegra186_asrc_set_audio_cif()
156 tegra_set_cif(asrc->regmap, reg, &cif_conf); in tegra186_asrc_set_audio_cif()
161 static int tegra186_asrc_in_hw_params(struct snd_pcm_substream *substream, in tegra186_asrc_in_hw_params()
165 struct device *dev = dai->dev; in tegra186_asrc_in_hw_params()
167 int ret, id = dai->id; in tegra186_asrc_in_hw_params()
169 /* Set input threshold */ in tegra186_asrc_in_hw_params()
170 regmap_write(asrc->regmap, in tegra186_asrc_in_hw_params()
171 ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, dai->id), in tegra186_asrc_in_hw_params()
172 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
175 ASRC_STREAM_REG(TEGRA186_ASRC_RX_CIF_CTRL, dai->id)); in tegra186_asrc_in_hw_params()
177 dev_err(dev, "Can't set ASRC RX%d CIF: %d\n", dai->id, ret); in tegra186_asrc_in_hw_params()
184 static int tegra186_asrc_out_hw_params(struct snd_pcm_substream *substream, in tegra186_asrc_out_hw_params()
188 struct device *dev = dai->dev; in tegra186_asrc_out_hw_params()
190 int ret, id = dai->id - 7; in tegra186_asrc_out_hw_params()
192 /* Set output threshold */ in tegra186_asrc_out_hw_params()
193 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
195 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
205 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
206 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
211 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
216 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
222 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
224 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
226 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
227 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
229 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
230 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
232 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
239 static int tegra186_asrc_get_ratio_source(struct snd_kcontrol *kcontrol, in tegra186_asrc_get_ratio_source()
243 (struct soc_enum *)kcontrol->private_value; in tegra186_asrc_get_ratio_source()
246 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_source()
248 ucontrol->value.enumerated.item[0] = asrc->lane[id].ratio_source; in tegra186_asrc_get_ratio_source()
253 static int tegra186_asrc_put_ratio_source(struct snd_kcontrol *kcontrol, in tegra186_asrc_put_ratio_source()
257 (struct soc_enum *)kcontrol->private_value; in tegra186_asrc_put_ratio_source()
260 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_source()
263 asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0]; in tegra186_asrc_put_ratio_source()
265 regmap_update_bits_check(asrc->regmap, asrc_private->reg, in tegra186_asrc_put_ratio_source()
267 asrc->lane[id].ratio_source, in tegra186_asrc_put_ratio_source()
273 static int tegra186_asrc_get_ratio_int(struct snd_kcontrol *kcontrol, in tegra186_asrc_get_ratio_int()
277 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_ratio_int()
280 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_int()
282 regmap_read(asrc->regmap, in tegra186_asrc_get_ratio_int()
284 &asrc->lane[id].int_part); in tegra186_asrc_get_ratio_int()
286 ucontrol->value.integer.value[0] = asrc->lane[id].int_part; in tegra186_asrc_get_ratio_int()
291 static int tegra186_asrc_put_ratio_int(struct snd_kcontrol *kcontrol, in tegra186_asrc_put_ratio_int()
295 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_ratio_int()
298 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_int()
301 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) { in tegra186_asrc_put_ratio_int()
302 dev_err(cmpnt->dev, in tegra186_asrc_put_ratio_int()
305 return -EINVAL; in tegra186_asrc_put_ratio_int()
308 asrc->lane[id].int_part = ucontrol->value.integer.value[0]; in tegra186_asrc_put_ratio_int()
310 regmap_update_bits_check(asrc->regmap, in tegra186_asrc_put_ratio_int()
314 asrc->lane[id].int_part, &change); in tegra186_asrc_put_ratio_int()
321 static int tegra186_asrc_get_ratio_frac(struct snd_kcontrol *kcontrol, in tegra186_asrc_get_ratio_frac()
325 (struct soc_mreg_control *)kcontrol->private_value; in tegra186_asrc_get_ratio_frac()
328 unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_frac()
330 regmap_read(asrc->regmap, in tegra186_asrc_get_ratio_frac()
332 &asrc->lane[id].frac_part); in tegra186_asrc_get_ratio_frac()
334 ucontrol->value.integer.value[0] = asrc->lane[id].frac_part; in tegra186_asrc_get_ratio_frac()
339 static int tegra186_asrc_put_ratio_frac(struct snd_kcontrol *kcontrol, in tegra186_asrc_put_ratio_frac()
343 (struct soc_mreg_control *)kcontrol->private_value; in tegra186_asrc_put_ratio_frac()
346 unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_frac()
349 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) { in tegra186_asrc_put_ratio_frac()
350 dev_err(cmpnt->dev, in tegra186_asrc_put_ratio_frac()
353 return -EINVAL; in tegra186_asrc_put_ratio_frac()
356 asrc->lane[id].frac_part = ucontrol->value.integer.value[0]; in tegra186_asrc_put_ratio_frac()
358 regmap_update_bits_check(asrc->regmap, in tegra186_asrc_put_ratio_frac()
362 asrc->lane[id].frac_part, &change); in tegra186_asrc_put_ratio_frac()
369 static int tegra186_asrc_get_hwcomp_disable(struct snd_kcontrol *kcontrol, in tegra186_asrc_get_hwcomp_disable()
373 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_hwcomp_disable()
376 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_hwcomp_disable()
378 ucontrol->value.integer.value[0] = asrc->lane[id].hwcomp_disable; in tegra186_asrc_get_hwcomp_disable()
383 static int tegra186_asrc_put_hwcomp_disable(struct snd_kcontrol *kcontrol, in tegra186_asrc_put_hwcomp_disable()
387 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_hwcomp_disable()
390 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_hwcomp_disable()
391 int value = ucontrol->value.integer.value[0]; in tegra186_asrc_put_hwcomp_disable()
393 if (value == asrc->lane[id].hwcomp_disable) in tegra186_asrc_put_hwcomp_disable()
396 asrc->lane[id].hwcomp_disable = value; in tegra186_asrc_put_hwcomp_disable()
401 static int tegra186_asrc_get_input_threshold(struct snd_kcontrol *kcontrol, in tegra186_asrc_get_input_threshold()
405 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_input_threshold()
408 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_input_threshold()
410 ucontrol->value.integer.value[0] = (asrc->lane[id].input_thresh & 0x3); in tegra186_asrc_get_input_threshold()
415 static int tegra186_asrc_put_input_threshold(struct snd_kcontrol *kcontrol, in tegra186_asrc_put_input_threshold()
419 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_input_threshold()
422 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_input_threshold()
423 int value = (asrc->lane[id].input_thresh & ~(0x3)) | in tegra186_asrc_put_input_threshold()
424 ucontrol->value.integer.value[0]; in tegra186_asrc_put_input_threshold()
426 if (value == asrc->lane[id].input_thresh) in tegra186_asrc_put_input_threshold()
429 asrc->lane[id].input_thresh = value; in tegra186_asrc_put_input_threshold()
434 static int tegra186_asrc_get_output_threshold(struct snd_kcontrol *kcontrol, in tegra186_asrc_get_output_threshold()
438 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_output_threshold()
441 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_output_threshold()
443 ucontrol->value.integer.value[0] = (asrc->lane[id].output_thresh & 0x3); in tegra186_asrc_get_output_threshold()
448 static int tegra186_asrc_put_output_threshold(struct snd_kcontrol *kcontrol, in tegra186_asrc_put_output_threshold()
452 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_output_threshold()
455 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_output_threshold()
456 int value = (asrc->lane[id].output_thresh & ~(0x3)) | in tegra186_asrc_put_output_threshold()
457 ucontrol->value.integer.value[0]; in tegra186_asrc_put_output_threshold()
459 if (value == asrc->lane[id].output_thresh) in tegra186_asrc_put_output_threshold()
462 asrc->lane[id].output_thresh = value; in tegra186_asrc_put_output_threshold()
467 static int tegra186_asrc_widget_event(struct snd_soc_dapm_widget *w, in tegra186_asrc_widget_event()
468 struct snd_kcontrol *kcontrol, int event) in tegra186_asrc_widget_event()
470 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in tegra186_asrc_widget_event()
471 struct tegra186_asrc *asrc = dev_get_drvdata(cmpnt->dev); in tegra186_asrc_widget_event()
472 unsigned int id = in tegra186_asrc_widget_event()
473 (w->reg - TEGRA186_ASRC_ENABLE) / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_widget_event()
475 regmap_write(asrc->regmap, in tegra186_asrc_widget_event()
492 .name = "ASRC-RX-CIF"#id, \
494 .stream_name = "RX" #id "-CIF-Playback",\
504 .stream_name = "RX" #id "-CIF-Capture", \
518 .name = "ASRC-TX-CIF"#id, \
520 .stream_name = "TX" #id "-CIF-Playback",\
530 .stream_name = "TX" #id "-CIF-Capture", \
609 { "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \
610 { "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname }, \
611 { "RX" #id, NULL, "RX" #id "-CIF-" sname }, \
613 { "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
614 { "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
615 { "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname },
622 { "RX7 XBAR-" sname, NULL, "RX7 XBAR-TX" }, \
623 { "RX7-CIF-" sname, NULL, "RX7 XBAR-" sname }, \
624 { "RX7", NULL, "RX7-CIF-" sname }, \
805 /* Input threshold for watermark fields */
806 SOC_SINGLE_EXT("Stream1 Input Threshold",
811 SOC_SINGLE_EXT("Stream2 Input Threshold",
816 SOC_SINGLE_EXT("Stream3 Input Threshold",
821 SOC_SINGLE_EXT("Stream4 Input Threshold",
826 SOC_SINGLE_EXT("Stream5 Input Threshold",
831 SOC_SINGLE_EXT("Stream6 Input Threshold",
836 /* Output threshold for watermark fields */
837 SOC_SINGLE_EXT("Stream1 Output Threshold",
842 SOC_SINGLE_EXT("Stream2 Output Threshold",
847 SOC_SINGLE_EXT("Stream3 Output Threshold",
852 SOC_SINGLE_EXT("Stream4 Output Threshold",
857 SOC_SINGLE_EXT("Stream5 Output Threshold",
862 SOC_SINGLE_EXT("Stream6 Output Threshold",
877 static bool tegra186_asrc_wr_reg(struct device *dev, unsigned int reg) in tegra186_asrc_wr_reg()
897 static bool tegra186_asrc_rd_reg(struct device *dev, unsigned int reg) in tegra186_asrc_rd_reg()
918 static bool tegra186_asrc_volatile_reg(struct device *dev, unsigned int reg) in tegra186_asrc_volatile_reg()
965 { .compatible = "nvidia,tegra186-asrc", .data = &soc_data_tegra186 },
966 { .compatible = "nvidia,tegra264-asrc", .data = &soc_data_tegra264 },
971 static int tegra186_asrc_platform_probe(struct platform_device *pdev) in tegra186_asrc_platform_probe()
973 struct device *dev = &pdev->dev; in tegra186_asrc_platform_probe()
976 unsigned int i; in tegra186_asrc_platform_probe()
977 int err; in tegra186_asrc_platform_probe()
981 return -ENOMEM; in tegra186_asrc_platform_probe()
989 asrc->regmap = devm_regmap_init_mmio(dev, regs, in tegra186_asrc_platform_probe()
991 if (IS_ERR(asrc->regmap)) { in tegra186_asrc_platform_probe()
993 return PTR_ERR(asrc->regmap); in tegra186_asrc_platform_probe()
996 asrc->soc_data = of_device_get_match_data(&pdev->dev); in tegra186_asrc_platform_probe()
998 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_platform_probe()
1000 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CFG, in tegra186_asrc_platform_probe()
1005 asrc->lane[i].ratio_source = TEGRA186_ASRC_RATIO_SOURCE_SW; in tegra186_asrc_platform_probe()
1006 asrc->lane[i].int_part = 1; in tegra186_asrc_platform_probe()
1007 asrc->lane[i].frac_part = 0; in tegra186_asrc_platform_probe()
1008 asrc->lane[i].hwcomp_disable = 0; in tegra186_asrc_platform_probe()
1009 asrc->lane[i].input_thresh = in tegra186_asrc_platform_probe()
1011 asrc->lane[i].output_thresh = in tegra186_asrc_platform_probe()
1030 pm_runtime_disable(&pdev->dev); in tegra186_asrc_platform_remove()
1041 .name = "tegra186-asrc",