Lines Matching +full:input +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
73 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
83 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
84 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
94 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
101 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
103 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
106 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
109 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
113 regmap_write(asrc->regmap, in tegra186_asrc_runtime_resume()
116 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
118 regmap_write(asrc->regmap, in tegra186_asrc_runtime_resume()
121 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
149 return -EINVAL; in tegra186_asrc_set_audio_cif()
157 tegra_set_cif(asrc->regmap, reg, &cif_conf); in tegra186_asrc_set_audio_cif()
166 struct device *dev = dai->dev; in tegra186_asrc_in_hw_params()
168 int ret, id = dai->id; in tegra186_asrc_in_hw_params()
170 /* Set input threshold */ in tegra186_asrc_in_hw_params()
171 regmap_write(asrc->regmap, in tegra186_asrc_in_hw_params()
172 ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, dai->id), in tegra186_asrc_in_hw_params()
173 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
176 ASRC_STREAM_REG(TEGRA186_ASRC_RX_CIF_CTRL, dai->id)); in tegra186_asrc_in_hw_params()
178 dev_err(dev, "Can't set ASRC RX%d CIF: %d\n", dai->id, ret); in tegra186_asrc_in_hw_params()
189 struct device *dev = dai->dev; in tegra186_asrc_out_hw_params()
191 int ret, id = dai->id - 7; in tegra186_asrc_out_hw_params()
193 /* Set output threshold */ in tegra186_asrc_out_hw_params()
194 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
196 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
206 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
207 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
212 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
217 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
223 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
225 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
227 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
228 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
230 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
231 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
233 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
244 (struct soc_enum *)kcontrol->private_value; in tegra186_asrc_get_ratio_source()
247 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_source()
249 ucontrol->value.enumerated.item[0] = asrc->lane[id].ratio_source; in tegra186_asrc_get_ratio_source()
258 (struct soc_enum *)kcontrol->private_value; in tegra186_asrc_put_ratio_source()
261 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_source()
264 asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0]; in tegra186_asrc_put_ratio_source()
266 regmap_update_bits_check(asrc->regmap, asrc_private->reg, in tegra186_asrc_put_ratio_source()
268 asrc->lane[id].ratio_source, in tegra186_asrc_put_ratio_source()
278 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_ratio_int()
281 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_int()
283 regmap_read(asrc->regmap, in tegra186_asrc_get_ratio_int()
285 &asrc->lane[id].int_part); in tegra186_asrc_get_ratio_int()
287 ucontrol->value.integer.value[0] = asrc->lane[id].int_part; in tegra186_asrc_get_ratio_int()
296 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_ratio_int()
299 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_int()
302 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) { in tegra186_asrc_put_ratio_int()
303 dev_err(cmpnt->dev, in tegra186_asrc_put_ratio_int()
306 return -EINVAL; in tegra186_asrc_put_ratio_int()
309 asrc->lane[id].int_part = ucontrol->value.integer.value[0]; in tegra186_asrc_put_ratio_int()
311 regmap_update_bits_check(asrc->regmap, in tegra186_asrc_put_ratio_int()
315 asrc->lane[id].int_part, &change); in tegra186_asrc_put_ratio_int()
326 (struct soc_mreg_control *)kcontrol->private_value; in tegra186_asrc_get_ratio_frac()
329 unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_frac()
331 regmap_read(asrc->regmap, in tegra186_asrc_get_ratio_frac()
333 &asrc->lane[id].frac_part); in tegra186_asrc_get_ratio_frac()
335 ucontrol->value.integer.value[0] = asrc->lane[id].frac_part; in tegra186_asrc_get_ratio_frac()
344 (struct soc_mreg_control *)kcontrol->private_value; in tegra186_asrc_put_ratio_frac()
347 unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_frac()
350 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) { in tegra186_asrc_put_ratio_frac()
351 dev_err(cmpnt->dev, in tegra186_asrc_put_ratio_frac()
354 return -EINVAL; in tegra186_asrc_put_ratio_frac()
357 asrc->lane[id].frac_part = ucontrol->value.integer.value[0]; in tegra186_asrc_put_ratio_frac()
359 regmap_update_bits_check(asrc->regmap, in tegra186_asrc_put_ratio_frac()
363 asrc->lane[id].frac_part, &change); in tegra186_asrc_put_ratio_frac()
374 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_hwcomp_disable()
377 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_hwcomp_disable()
379 ucontrol->value.integer.value[0] = asrc->lane[id].hwcomp_disable; in tegra186_asrc_get_hwcomp_disable()
388 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_hwcomp_disable()
391 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_hwcomp_disable()
392 int value = ucontrol->value.integer.value[0]; in tegra186_asrc_put_hwcomp_disable()
394 if (value == asrc->lane[id].hwcomp_disable) in tegra186_asrc_put_hwcomp_disable()
397 asrc->lane[id].hwcomp_disable = value; in tegra186_asrc_put_hwcomp_disable()
406 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_input_threshold()
409 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_input_threshold()
411 ucontrol->value.integer.value[0] = (asrc->lane[id].input_thresh & 0x3); in tegra186_asrc_get_input_threshold()
420 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_input_threshold()
423 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_input_threshold()
424 int value = (asrc->lane[id].input_thresh & ~(0x3)) | in tegra186_asrc_put_input_threshold()
425 ucontrol->value.integer.value[0]; in tegra186_asrc_put_input_threshold()
427 if (value == asrc->lane[id].input_thresh) in tegra186_asrc_put_input_threshold()
430 asrc->lane[id].input_thresh = value; in tegra186_asrc_put_input_threshold()
439 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_output_threshold()
442 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_output_threshold()
444 ucontrol->value.integer.value[0] = (asrc->lane[id].output_thresh & 0x3); in tegra186_asrc_get_output_threshold()
453 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_output_threshold()
456 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_output_threshold()
457 int value = (asrc->lane[id].output_thresh & ~(0x3)) | in tegra186_asrc_put_output_threshold()
458 ucontrol->value.integer.value[0]; in tegra186_asrc_put_output_threshold()
460 if (value == asrc->lane[id].output_thresh) in tegra186_asrc_put_output_threshold()
463 asrc->lane[id].output_thresh = value; in tegra186_asrc_put_output_threshold()
471 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in tegra186_asrc_widget_event()
472 struct tegra186_asrc *asrc = dev_get_drvdata(cmpnt->dev); in tegra186_asrc_widget_event()
474 (w->reg - TEGRA186_ASRC_ENABLE) / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_widget_event()
476 regmap_write(asrc->regmap, in tegra186_asrc_widget_event()
493 .name = "ASRC-RX-CIF"#id, \
495 .stream_name = "RX" #id "-CIF-Playback",\
505 .stream_name = "RX" #id "-CIF-Capture", \
519 .name = "ASRC-TX-CIF"#id, \
521 .stream_name = "TX" #id "-CIF-Playback",\
531 .stream_name = "TX" #id "-CIF-Capture", \
544 /* ASRC Input */
610 { "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \
611 { "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname }, \
612 { "RX" #id, NULL, "RX" #id "-CIF-" sname }, \
614 { "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
615 { "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
616 { "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname },
623 { "RX7 XBAR-" sname, NULL, "RX7 XBAR-TX" }, \
624 { "RX7-CIF-" sname, NULL, "RX7 XBAR-" sname }, \
625 { "RX7", NULL, "RX7-CIF-" sname }, \
775 /* Disable HW managed overflow/underflow issue at input and output */
806 /* Input threshold for watermark fields */
807 SOC_SINGLE_EXT("Stream1 Input Threshold",
812 SOC_SINGLE_EXT("Stream2 Input Threshold",
817 SOC_SINGLE_EXT("Stream3 Input Threshold",
822 SOC_SINGLE_EXT("Stream4 Input Threshold",
827 SOC_SINGLE_EXT("Stream5 Input Threshold",
832 SOC_SINGLE_EXT("Stream6 Input Threshold",
837 /* Output threshold for watermark fields */
838 SOC_SINGLE_EXT("Stream1 Output Threshold",
843 SOC_SINGLE_EXT("Stream2 Output Threshold",
848 SOC_SINGLE_EXT("Stream3 Output Threshold",
853 SOC_SINGLE_EXT("Stream4 Output Threshold",
858 SOC_SINGLE_EXT("Stream5 Output Threshold",
863 SOC_SINGLE_EXT("Stream6 Output Threshold",
958 { .compatible = "nvidia,tegra186-asrc" },
965 struct device *dev = &pdev->dev; in tegra186_asrc_platform_probe()
973 return -ENOMEM; in tegra186_asrc_platform_probe()
981 asrc->regmap = devm_regmap_init_mmio(dev, regs, in tegra186_asrc_platform_probe()
983 if (IS_ERR(asrc->regmap)) { in tegra186_asrc_platform_probe()
985 return PTR_ERR(asrc->regmap); in tegra186_asrc_platform_probe()
988 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_platform_probe()
990 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CFG, in tegra186_asrc_platform_probe()
995 asrc->lane[i].ratio_source = TEGRA186_ASRC_RATIO_SOURCE_SW; in tegra186_asrc_platform_probe()
996 asrc->lane[i].int_part = 1; in tegra186_asrc_platform_probe()
997 asrc->lane[i].frac_part = 0; in tegra186_asrc_platform_probe()
998 asrc->lane[i].hwcomp_disable = 0; in tegra186_asrc_platform_probe()
999 asrc->lane[i].input_thresh = in tegra186_asrc_platform_probe()
1001 asrc->lane[i].output_thresh = in tegra186_asrc_platform_probe()
1020 pm_runtime_disable(&pdev->dev); in tegra186_asrc_platform_remove()
1032 .name = "tegra186-asrc",