Lines Matching refs:SUN4I_I2S_CLK_DIV_REG
73 #define SUN4I_I2S_CLK_DIV_REG 0x24 macro
400 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, in sun4i_i2s_set_clk_rate()
1219 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1232 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1246 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1367 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1386 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1410 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1429 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
1448 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1467 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
1486 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),