24 #define SUN4I_I2S_CTRL_REG		0x00
29 #define SUN4I_I2S_CTRL_MODE_MASTER			(0 << 5)
32 #define SUN4I_I2S_CTRL_GL_EN			BIT(0)
34 #define SUN4I_I2S_FMT0_REG		0x04
37 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL		(0 << 7)
40 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL		(0 << 6)
45 #define SUN4I_I2S_FMT0_FMT_MASK			GENMASK(1, 0)
46 #define SUN4I_I2S_FMT0_FMT_RIGHT_J			(2 << 0)
47 #define SUN4I_I2S_FMT0_FMT_LEFT_J			(1 << 0)
48 #define SUN4I_I2S_FMT0_FMT_I2S				(0 << 0)
50 #define SUN4I_I2S_FMT1_REG		0x08
54 #define SUN4I_I2S_FIFO_TX_REG		0x0c
55 #define SUN4I_I2S_FIFO_RX_REG		0x10
57 #define SUN4I_I2S_FIFO_CTRL_REG		0x14
62 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK	GENMASK(1, 0)
65 #define SUN4I_I2S_FIFO_STA_REG		0x18
67 #define SUN4I_I2S_DMA_INT_CTRL_REG	0x1c
71 #define SUN4I_I2S_INT_STA_REG		0x20
73 #define SUN4I_I2S_CLK_DIV_REG		0x24
77 #define SUN4I_I2S_CLK_DIV_MCLK_MASK		GENMASK(3, 0)
78 #define SUN4I_I2S_CLK_DIV_MCLK(mclk)			((mclk) << 0)
80 #define SUN4I_I2S_TX_CNT_REG		0x28
81 #define SUN4I_I2S_RX_CNT_REG		0x2c
83 #define SUN4I_I2S_TX_CHAN_SEL_REG	0x30
84 #define SUN4I_I2S_CHAN_SEL_MASK			GENMASK(2, 0)
85 #define SUN4I_I2S_CHAN_SEL(num_chan)		(((num_chan) - 1) << 0)
87 #define SUN4I_I2S_TX_CHAN_MAP_REG	0x34
90 #define SUN4I_I2S_RX_CHAN_SEL_REG	0x38
91 #define SUN4I_I2S_RX_CHAN_MAP_REG	0x3c
100 #define SUN8I_I2S_CTRL_MODE_PCM			(0 << 4)
104 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_START_LOW		(0 << 19)
109 #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL		(0 << 7)
114 #define SUN8I_I2S_INT_STA_REG		0x0c
115 #define SUN8I_I2S_FIFO_TX_REG		0x20
117 #define SUN8I_I2S_CHAN_CFG_REG		0x30
120 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK	GENMASK(3, 0)
123 #define SUN8I_I2S_TX_CHAN_MAP_REG	0x44
124 #define SUN8I_I2S_TX_CHAN_SEL_REG	0x34
130 #define SUN8I_I2S_RX_CHAN_SEL_REG	0x54
131 #define SUN8I_I2S_RX_CHAN_MAP_REG	0x58
138 #define SUN50I_H6_I2S_TX_CHAN_EN_MASK		GENMASK(15, 0)
141 #define SUN50I_H6_I2S_TX_CHAN_SEL_REG(pin)	(0x34 + 4 * (pin))
142 #define SUN50I_H6_I2S_TX_CHAN_MAP0_REG(pin)	(0x44 + 8 * (pin))
143 #define SUN50I_H6_I2S_TX_CHAN_MAP1_REG(pin)	(0x48 + 8 * (pin))
145 #define SUN50I_H6_I2S_RX_CHAN_SEL_REG	0x64
146 #define SUN50I_H6_I2S_RX_CHAN_MAP0_REG	0x68
147 #define SUN50I_H6_I2S_RX_CHAN_MAP1_REG	0x6C
149 #define SUN50I_R329_I2S_RX_CHAN_MAP0_REG 0x68
150 #define SUN50I_R329_I2S_RX_CHAN_MAP1_REG 0x6c
151 #define SUN50I_R329_I2S_RX_CHAN_MAP2_REG 0x70
152 #define SUN50I_R329_I2S_RX_CHAN_MAP3_REG 0x74
239 	{ .div = 2, .val = 0 },
249 	{ .div = 1, .val = 0 },
298 	for (i = 0; i < i2s->variant->num_bclk_dividers; i++) {  in sun4i_i2s_get_bclk_div()
316 	for (i = 0; i < i2s->variant->num_mclk_dividers; i++) {  in sun4i_i2s_get_mclk_div()
331 	for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)  in sun4i_i2s_oversample_is_valid()
389 	if (bclk_div < 0) {  in sun4i_i2s_set_clk_rate()
395 	if (mclk_div < 0) {  in sun4i_i2s_set_clk_rate()
406 	return 0;  in sun4i_i2s_set_clk_rate()
413 		return 0;  in sun4i_i2s_get_sr()
427 		return 0;  in sun4i_i2s_get_wss()
466 	regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);  in sun4i_i2s_set_chan_cfg()
467 	regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210);  in sun4i_i2s_set_chan_cfg()
477 	return 0;  in sun4i_i2s_set_chan_cfg()
487 	regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);  in sun8i_i2s_set_chan_cfg()
488 	regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);  in sun8i_i2s_set_chan_cfg()
529 	return 0;  in sun8i_i2s_set_chan_cfg()
539 	regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98);  in sun50i_h6_i2s_set_chan_cfg()
540 	regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210);  in sun50i_h6_i2s_set_chan_cfg()
542 		regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C);  in sun50i_h6_i2s_set_chan_cfg()
543 		regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908);  in sun50i_h6_i2s_set_chan_cfg()
544 		regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504);  in sun50i_h6_i2s_set_chan_cfg()
545 		regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100);  in sun50i_h6_i2s_set_chan_cfg()
547 		regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);  in sun50i_h6_i2s_set_chan_cfg()
548 		regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);  in sun50i_h6_i2s_set_chan_cfg()
552 	regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),  in sun50i_h6_i2s_set_chan_cfg()
586 	regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),  in sun50i_h6_i2s_set_chan_cfg()
590 	return 0;  in sun50i_h6_i2s_set_chan_cfg()
614 	if (ret < 0) {  in sun4i_i2s_hw_params()
641 	if (sr < 0)  in sun4i_i2s_hw_params()
645 	if (wss < 0)  in sun4i_i2s_hw_params()
676 		val = 0;  in sun4i_i2s_set_soc_fmt()
726 	return 0;  in sun4i_i2s_set_soc_fmt()
746 		offset = 0;  in sun8i_i2s_set_soc_fmt()
758 		offset = 0;  in sun8i_i2s_set_soc_fmt()
764 		offset = 0;  in sun8i_i2s_set_soc_fmt()
818 		val = 0;  in sun8i_i2s_set_soc_fmt()
829 	/* Set sign extension to pad out LSB with 0 */  in sun8i_i2s_set_soc_fmt()
832 			   SUN8I_I2S_FMT1_REG_SEXT(0));  in sun8i_i2s_set_soc_fmt()
834 	return 0;  in sun8i_i2s_set_soc_fmt()
854 		offset = 0;  in sun50i_h6_i2s_set_soc_fmt()
866 		offset = 0;  in sun50i_h6_i2s_set_soc_fmt()
872 		offset = 0;  in sun50i_h6_i2s_set_soc_fmt()
927 		val = 0;  in sun50i_h6_i2s_set_soc_fmt()
938 	/* Set sign extension to pad out LSB with 0 */  in sun50i_h6_i2s_set_soc_fmt()
941 			   SUN8I_I2S_FMT1_REG_SEXT(0));  in sun50i_h6_i2s_set_soc_fmt()
943 	return 0;  in sun50i_h6_i2s_set_soc_fmt()
959 	return 0;  in sun4i_i2s_set_fmt()
970 	regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);  in sun4i_i2s_start_capture()
991 	regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);  in sun4i_i2s_start_playback()
1009 			   0);  in sun4i_i2s_stop_capture()
1014 			   0);  in sun4i_i2s_stop_capture()
1022 			   0);  in sun4i_i2s_stop_playback()
1027 			   0);  in sun4i_i2s_stop_playback()
1058 	return 0;  in sun4i_i2s_trigger()
1066 	if (clk_id != 0)  in sun4i_i2s_set_sysclk()
1071 	return 0;  in sun4i_i2s_set_sysclk()
1086 	return 0;  in sun4i_i2s_set_tdm_slot()
1097 	return 0;  in sun4i_i2s_dai_probe()
1214 	{ SUN4I_I2S_CTRL_REG, 0x00000000 },
1215 	{ SUN4I_I2S_FMT0_REG, 0x0000000c },
1216 	{ SUN4I_I2S_FMT1_REG, 0x00004020 },
1217 	{ SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
1218 	{ SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
1219 	{ SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1220 	{ SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
1221 	{ SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
1222 	{ SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
1223 	{ SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
1227 	{ SUN4I_I2S_CTRL_REG, 0x00060000 },
1228 	{ SUN4I_I2S_FMT0_REG, 0x00000033 },
1229 	{ SUN4I_I2S_FMT1_REG, 0x00000030 },
1230 	{ SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
1231 	{ SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
1232 	{ SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1233 	{ SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
1234 	{ SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
1235 	{ SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
1236 	{ SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
1237 	{ SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
1241 	{ SUN4I_I2S_CTRL_REG, 0x00060000 },
1242 	{ SUN4I_I2S_FMT0_REG, 0x00000033 },
1243 	{ SUN4I_I2S_FMT1_REG, 0x00000030 },
1244 	{ SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
1245 	{ SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
1246 	{ SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
1247 	{ SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
1248 	{ SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 0x00000000 },
1249 	{ SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0x00000000 },
1250 	{ SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x00000000 },
1251 	{ SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 },
1252 	{ SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 },
1253 	{ SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 },
1323 			   SUN4I_I2S_CTRL_SDO_EN(0));  in sun4i_i2s_runtime_resume()
1331 	return 0;  in sun4i_i2s_runtime_resume()
1346 			   SUN4I_I2S_CTRL_SDO_EN_MASK, 0);  in sun4i_i2s_runtime_suspend()
1350 			   SUN4I_I2S_CTRL_GL_EN, 0);  in sun4i_i2s_runtime_suspend()
1356 	return 0;  in sun4i_i2s_runtime_suspend()
1430 	.field_fmt_wss		= REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
1468 	.field_fmt_wss		= REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
1487 	.field_fmt_wss		= REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
1523 	return 0;  in sun4i_i2s_init_regmap_fields()
1538 	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in sun4i_i2s_probe()
1542 	irq = platform_get_irq(pdev, 0);  in sun4i_i2s_probe()
1543 	if (irq < 0)  in sun4i_i2s_probe()
1608 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);  in sun4i_i2s_probe()
1622 	return 0;  in sun4i_i2s_probe()