Lines Matching +full:sub +full:- +full:block
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
10 #include <linux/clk-provider.h>
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
65 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
68 * @regmap_config: SAI sub block register map configuration pointer
73 * @pdata: SAI block parent data pointer
78 * @mclk_rate: SAI block master clock frequency (Hz). set at init
79 * @id: SAI sub block id corresponding to sub-block A or B
80 * @dir: SAI block direction (playback or capture). set at init
81 * @master: SAI block mode flag. (true=master, false=slave) set at init
83 * @fmt: SAI block format. relevant only for custom protocols. set at init
84 * @sync: SAI block synchronization mode. (none, internal or external)
85 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
86 * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
192 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_up()
196 ret = regmap_update_bits(sai->regmap, reg, mask, val); in stm32_sai_sub_reg_up()
198 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_up()
209 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_wr()
213 ret = regmap_write_bits(sai->regmap, reg, mask, val); in stm32_sai_sub_reg_wr()
215 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_wr()
225 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_rd()
229 ret = regmap_read(sai->regmap, reg, val); in stm32_sai_sub_reg_rd()
231 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_rd()
263 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in snd_pcm_iec958_info()
264 uinfo->count = 1; in snd_pcm_iec958_info()
274 mutex_lock(&sai->ctrl_lock); in snd_pcm_iec958_get()
275 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); in snd_pcm_iec958_get()
276 mutex_unlock(&sai->ctrl_lock); in snd_pcm_iec958_get()
286 mutex_lock(&sai->ctrl_lock); in snd_pcm_iec958_put()
287 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); in snd_pcm_iec958_put()
288 mutex_unlock(&sai->ctrl_lock); in snd_pcm_iec958_put()
316 int version = sai->pdata->conf.version; in stm32_sai_get_clk_div()
321 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); in stm32_sai_get_clk_div()
322 return -EINVAL; in stm32_sai_get_clk_div()
324 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); in stm32_sai_get_clk_div()
327 dev_dbg(&sai->pdev->dev, in stm32_sai_get_clk_div()
337 int version = sai->pdata->conf.version; in stm32_sai_set_clk_div()
341 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); in stm32_sai_set_clk_div()
342 return -EINVAL; in stm32_sai_set_clk_div()
349 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); in stm32_sai_set_clk_div()
357 struct platform_device *pdev = sai->pdev; in stm32_sai_set_parent_clock()
358 struct clk *parent_clk = sai->pdata->clk_x8k; in stm32_sai_set_parent_clock()
362 parent_clk = sai->pdata->clk_x11k; in stm32_sai_set_parent_clock()
364 ret = clk_set_parent(sai->sai_ck, parent_clk); in stm32_sai_set_parent_clock()
366 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", in stm32_sai_set_parent_clock()
367 ret, ret == -EBUSY ? in stm32_sai_set_parent_clock()
377 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_round_rate()
384 mclk->freq = *prate / div; in stm32_sai_mclk_round_rate()
386 return mclk->freq; in stm32_sai_mclk_round_rate()
394 return mclk->freq; in stm32_sai_mclk_recalc_rate()
401 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_set_rate()
412 mclk->freq = rate; in stm32_sai_mclk_set_rate()
420 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_enable()
422 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); in stm32_sai_mclk_enable()
431 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_disable()
433 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); in stm32_sai_mclk_disable()
450 struct device *dev = &sai->pdev->dev; in stm32_sai_add_mclk_provider()
451 const char *pname = __clk_get_name(sai->sai_ck); in stm32_sai_add_mclk_provider()
457 return -ENOMEM; in stm32_sai_add_mclk_provider()
462 return -ENOMEM; in stm32_sai_add_mclk_provider()
469 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { in stm32_sai_add_mclk_provider()
475 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); in stm32_sai_add_mclk_provider()
476 mclk->sai_data = sai; in stm32_sai_add_mclk_provider()
477 hw = &mclk->hw; in stm32_sai_add_mclk_provider()
480 ret = devm_clk_hw_register(&sai->pdev->dev, hw); in stm32_sai_add_mclk_provider()
485 sai->sai_mclk = hw->clk; in stm32_sai_add_mclk_provider()
494 struct platform_device *pdev = sai->pdev; in stm32_sai_isr()
508 if (!sai->substream) { in stm32_sai_isr()
509 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); in stm32_sai_isr()
514 dev_err(&pdev->dev, "IRQ %s\n", in stm32_sai_isr()
520 dev_dbg(&pdev->dev, "IRQ mute detected\n"); in stm32_sai_isr()
523 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); in stm32_sai_isr()
528 dev_err(&pdev->dev, "IRQ Codec not ready\n"); in stm32_sai_isr()
531 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); in stm32_sai_isr()
536 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); in stm32_sai_isr()
540 spin_lock(&sai->irq_lock); in stm32_sai_isr()
541 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) in stm32_sai_isr()
542 snd_pcm_stop_xrun(sai->substream); in stm32_sai_isr()
543 spin_unlock(&sai->irq_lock); in stm32_sai_isr()
554 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { in stm32_sai_set_sysclk()
564 if (sai->mclk_rate) { in stm32_sai_set_sysclk()
565 clk_rate_exclusive_put(sai->sai_mclk); in stm32_sai_set_sysclk()
566 sai->mclk_rate = 0; in stm32_sai_set_sysclk()
576 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); in stm32_sai_set_sysclk()
578 dev_err(cpu_dai->dev, in stm32_sai_set_sysclk()
579 ret == -EBUSY ? in stm32_sai_set_sysclk()
585 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); in stm32_sai_set_sysclk()
586 sai->mclk_rate = freq; in stm32_sai_set_sysclk()
599 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); in stm32_sai_set_dai_tdm_slot()
603 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", in stm32_sai_set_dai_tdm_slot()
619 SAI_XSLOTR_NBSLOT_SET(slots - 1); in stm32_sai_set_dai_tdm_slot()
624 sai->slot_mask = tx_mask; in stm32_sai_set_dai_tdm_slot()
629 sai->slot_mask = rx_mask; in stm32_sai_set_dai_tdm_slot()
637 sai->slot_width = slot_width; in stm32_sai_set_dai_tdm_slot()
638 sai->slots = slots; in stm32_sai_set_dai_tdm_slot()
650 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); in stm32_sai_set_dai_fmt()
685 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", in stm32_sai_set_dai_fmt()
687 return -EINVAL; in stm32_sai_set_dai_fmt()
710 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", in stm32_sai_set_dai_fmt()
712 return -EINVAL; in stm32_sai_set_dai_fmt()
724 sai->master = false; in stm32_sai_set_dai_fmt()
727 sai->master = true; in stm32_sai_set_dai_fmt()
730 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", in stm32_sai_set_dai_fmt()
732 return -EINVAL; in stm32_sai_set_dai_fmt()
735 /* Set slave mode if sub-block is synchronized with another SAI */ in stm32_sai_set_dai_fmt()
736 if (sai->sync) { in stm32_sai_set_dai_fmt()
737 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); in stm32_sai_set_dai_fmt()
739 sai->master = false; in stm32_sai_set_dai_fmt()
747 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_set_dai_fmt()
751 sai->fmt = fmt; in stm32_sai_set_dai_fmt()
763 spin_lock_irqsave(&sai->irq_lock, flags); in stm32_sai_startup()
764 sai->substream = substream; in stm32_sai_startup()
765 spin_unlock_irqrestore(&sai->irq_lock, flags); in stm32_sai_startup()
768 snd_pcm_hw_constraint_mask64(substream->runtime, in stm32_sai_startup()
771 snd_pcm_hw_constraint_single(substream->runtime, in stm32_sai_startup()
775 ret = clk_prepare_enable(sai->sai_ck); in stm32_sai_startup()
777 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); in stm32_sai_startup()
792 if (sai->master) in stm32_sai_startup()
822 sai->spdif_frm_cnt = 0; in stm32_sai_set_config()
839 dev_err(cpu_dai->dev, "Data format not supported\n"); in stm32_sai_set_config()
840 return -EINVAL; in stm32_sai_set_config()
844 if ((sai->slots == 2) && (params_channels(params) == 1)) in stm32_sai_set_config()
849 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_set_config()
869 sai->slot_width = sai->data_size; in stm32_sai_set_slots()
871 if (sai->slot_width < sai->data_size) { in stm32_sai_set_slots()
872 dev_err(cpu_dai->dev, in stm32_sai_set_slots()
874 sai->data_size); in stm32_sai_set_slots()
875 return -EINVAL; in stm32_sai_set_slots()
879 if (!sai->slots) in stm32_sai_set_slots()
880 sai->slots = 2; in stm32_sai_set_slots()
885 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); in stm32_sai_set_slots()
889 sai->slot_mask = (1 << sai->slots) - 1; in stm32_sai_set_slots()
892 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); in stm32_sai_set_slots()
895 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", in stm32_sai_set_slots()
896 sai->slots, sai->slot_width); in stm32_sai_set_slots()
907 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; in stm32_sai_set_frame()
908 sai->fs_length = sai->slot_width * sai->slots; in stm32_sai_set_frame()
910 fs_active = sai->fs_length / 2; in stm32_sai_set_frame()
915 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); in stm32_sai_set_frame()
916 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); in stm32_sai_set_frame()
919 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", in stm32_sai_set_frame()
920 sai->fs_length, fs_active); in stm32_sai_set_frame()
924 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { in stm32_sai_set_frame()
925 offset = sai->slot_width - sai->data_size; in stm32_sai_set_frame()
935 unsigned char *cs = sai->iec958.status; in stm32_sai_init_iec958_status()
950 mutex_lock(&sai->ctrl_lock); in stm32_sai_set_iec958_status()
951 switch (runtime->rate) { in stm32_sai_set_iec958_status()
953 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; in stm32_sai_set_iec958_status()
956 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; in stm32_sai_set_iec958_status()
959 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; in stm32_sai_set_iec958_status()
962 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; in stm32_sai_set_iec958_status()
965 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; in stm32_sai_set_iec958_status()
968 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; in stm32_sai_set_iec958_status()
971 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; in stm32_sai_set_iec958_status()
974 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; in stm32_sai_set_iec958_status()
977 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; in stm32_sai_set_iec958_status()
980 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; in stm32_sai_set_iec958_status()
983 mutex_unlock(&sai->ctrl_lock); in stm32_sai_set_iec958_status()
995 if (!sai->sai_mclk) { in stm32_sai_configure_clock()
1000 sai_clk_rate = clk_get_rate(sai->sai_ck); in stm32_sai_configure_clock()
1002 if (STM_SAI_IS_F4(sai->pdata)) { in stm32_sai_configure_clock()
1010 if (!sai->mclk_rate) in stm32_sai_configure_clock()
1013 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { in stm32_sai_configure_clock()
1015 2 * sai->mclk_rate); in stm32_sai_configure_clock()
1035 if (sai->mclk_rate) { in stm32_sai_configure_clock()
1036 mclk_ratio = sai->mclk_rate / rate; in stm32_sai_configure_clock()
1040 dev_err(cpu_dai->dev, in stm32_sai_configure_clock()
1043 return -EINVAL; in stm32_sai_configure_clock()
1051 sai->mclk_rate); in stm32_sai_configure_clock()
1055 /* mclk-fs not set, master clock not active */ in stm32_sai_configure_clock()
1056 den = sai->fs_length * params_rate(params); in stm32_sai_configure_clock()
1075 sai->data_size = params_width(params); in stm32_sai_hw_params()
1079 substream->runtime->rate = params_rate(params); in stm32_sai_hw_params()
1080 stm32_sai_set_iec958_status(sai, substream->runtime); in stm32_sai_hw_params()
1092 if (sai->master) in stm32_sai_hw_params()
1108 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); in stm32_sai_trigger()
1117 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_trigger()
1122 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); in stm32_sai_trigger()
1135 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_trigger()
1138 sai->spdif_frm_cnt = 0; in stm32_sai_trigger()
1141 return -EINVAL; in stm32_sai_trigger()
1155 clk_disable_unprepare(sai->sai_ck); in stm32_sai_shutdown()
1157 spin_lock_irqsave(&sai->irq_lock, flags); in stm32_sai_shutdown()
1158 sai->substream = NULL; in stm32_sai_shutdown()
1159 spin_unlock_irqrestore(&sai->irq_lock, flags); in stm32_sai_shutdown()
1165 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_pcm_new()
1169 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); in stm32_sai_pcm_new()
1170 knew.device = rtd->pcm->device; in stm32_sai_pcm_new()
1171 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); in stm32_sai_pcm_new()
1179 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_dai_probe()
1182 sai->cpu_dai = cpu_dai; in stm32_sai_dai_probe()
1184 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); in stm32_sai_dai_probe()
1187 * as it allows bytes, half-word and words transfers. (See DMA fifos in stm32_sai_dai_probe()
1190 sai->dma_params.maxburst = 4; in stm32_sai_dai_probe()
1191 if (sai->pdata->conf.fifo_size < 8) in stm32_sai_dai_probe()
1192 sai->dma_params.maxburst = 1; in stm32_sai_dai_probe()
1194 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; in stm32_sai_dai_probe()
1197 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); in stm32_sai_dai_probe()
1199 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); in stm32_sai_dai_probe()
1210 if (sai->sync == SAI_SYNC_EXTERNAL) { in stm32_sai_dai_probe()
1212 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, in stm32_sai_dai_probe()
1213 sai->synco, sai->synci); in stm32_sai_dai_probe()
1219 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); in stm32_sai_dai_probe()
1251 struct snd_pcm_runtime *runtime = substream->runtime; in stm32_sai_pcm_process_spdif()
1254 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_pcm_process_spdif()
1255 int *ptr = (int *)(runtime->dma_area + hwoff + in stm32_sai_pcm_process_spdif()
1256 channel * (runtime->dma_bytes / runtime->channels)); in stm32_sai_pcm_process_spdif()
1258 unsigned int frm_cnt = sai->spdif_frm_cnt; in stm32_sai_pcm_process_spdif()
1267 mask = 1 << (frm_cnt - (byte << 3)); in stm32_sai_pcm_process_spdif()
1268 if (sai->iec958.status[byte] & mask) in stm32_sai_pcm_process_spdif()
1277 } while (--cnt); in stm32_sai_pcm_process_spdif()
1278 sai->spdif_frm_cnt = frm_cnt; in stm32_sai_pcm_process_spdif()
1348 .name = "stm32-sai",
1353 { .compatible = "st,stm32-sai-sub-a",
1355 { .compatible = "st,stm32-sai-sub-b",
1364 struct device_node *np = pdev->dev.of_node; in stm32_sai_sub_parse_of()
1371 return -ENODEV; in stm32_sai_sub_parse_of()
1377 sai->phys_addr = res->start; in stm32_sai_sub_parse_of()
1379 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; in stm32_sai_sub_parse_of()
1380 /* Note: PDM registers not available for sub-block B */ in stm32_sai_sub_parse_of()
1382 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; in stm32_sai_sub_parse_of()
1389 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, in stm32_sai_sub_parse_of()
1390 sai->regmap_config); in stm32_sai_sub_parse_of()
1391 if (IS_ERR(sai->regmap)) in stm32_sai_sub_parse_of()
1392 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap), in stm32_sai_sub_parse_of()
1396 if (of_property_match_string(np, "dma-names", "tx") >= 0) { in stm32_sai_sub_parse_of()
1397 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; in stm32_sai_sub_parse_of()
1398 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { in stm32_sai_sub_parse_of()
1399 sai->dir = SNDRV_PCM_STREAM_CAPTURE; in stm32_sai_sub_parse_of()
1401 dev_err(&pdev->dev, "Unsupported direction\n"); in stm32_sai_sub_parse_of()
1402 return -EINVAL; in stm32_sai_sub_parse_of()
1406 sai->spdif = false; in stm32_sai_sub_parse_of()
1409 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { in stm32_sai_sub_parse_of()
1410 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); in stm32_sai_sub_parse_of()
1411 return -EINVAL; in stm32_sai_sub_parse_of()
1414 sai->spdif = true; in stm32_sai_sub_parse_of()
1415 sai->master = true; in stm32_sai_sub_parse_of()
1421 if (ret < 0 && ret != -ENOENT) { in stm32_sai_sub_parse_of()
1422 dev_err(&pdev->dev, "Failed to get st,sync property\n"); in stm32_sai_sub_parse_of()
1426 sai->sync = SAI_SYNC_NONE; in stm32_sai_sub_parse_of()
1429 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); in stm32_sai_sub_parse_of()
1431 return -EINVAL; in stm32_sai_sub_parse_of()
1434 sai->np_sync_provider = of_get_parent(args.np); in stm32_sai_sub_parse_of()
1435 if (!sai->np_sync_provider) { in stm32_sai_sub_parse_of()
1436 dev_err(&pdev->dev, "%pOFn parent node not found\n", in stm32_sai_sub_parse_of()
1439 return -ENODEV; in stm32_sai_sub_parse_of()
1442 sai->sync = SAI_SYNC_INTERNAL; in stm32_sai_sub_parse_of()
1443 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { in stm32_sai_sub_parse_of()
1445 dev_err(&pdev->dev, in stm32_sai_sub_parse_of()
1448 return -EINVAL; in stm32_sai_sub_parse_of()
1450 sai->sync = SAI_SYNC_EXTERNAL; in stm32_sai_sub_parse_of()
1452 sai->synci = args.args[0]; in stm32_sai_sub_parse_of()
1453 if (sai->synci < 1 || in stm32_sai_sub_parse_of()
1454 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { in stm32_sai_sub_parse_of()
1455 dev_err(&pdev->dev, "Wrong SAI index\n"); in stm32_sai_sub_parse_of()
1457 return -EINVAL; in stm32_sai_sub_parse_of()
1461 "st,stm32-sai-sub-a") >= 0) in stm32_sai_sub_parse_of()
1462 sai->synco = STM_SAI_SYNC_OUT_A; in stm32_sai_sub_parse_of()
1465 "st,stm32-sai-sub-b") >= 0) in stm32_sai_sub_parse_of()
1466 sai->synco = STM_SAI_SYNC_OUT_B; in stm32_sai_sub_parse_of()
1468 if (!sai->synco) { in stm32_sai_sub_parse_of()
1469 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); in stm32_sai_sub_parse_of()
1471 return -EINVAL; in stm32_sai_sub_parse_of()
1475 dev_dbg(&pdev->dev, "%s synchronized with %s\n", in stm32_sai_sub_parse_of()
1476 pdev->name, args.np->full_name); in stm32_sai_sub_parse_of()
1480 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); in stm32_sai_sub_parse_of()
1481 if (IS_ERR(sai->sai_ck)) in stm32_sai_sub_parse_of()
1482 return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck), in stm32_sai_sub_parse_of()
1485 ret = clk_prepare(sai->pdata->pclk); in stm32_sai_sub_parse_of()
1489 if (STM_SAI_IS_F4(sai->pdata)) in stm32_sai_sub_parse_of()
1493 if (of_property_present(np, "#clock-cells")) { in stm32_sai_sub_parse_of()
1498 sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK"); in stm32_sai_sub_parse_of()
1499 if (IS_ERR(sai->sai_mclk)) in stm32_sai_sub_parse_of()
1500 return PTR_ERR(sai->sai_mclk); in stm32_sai_sub_parse_of()
1512 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); in stm32_sai_sub_probe()
1514 return -ENOMEM; in stm32_sai_sub_probe()
1516 sai->id = (uintptr_t)device_get_match_data(&pdev->dev); in stm32_sai_sub_probe()
1518 sai->pdev = pdev; in stm32_sai_sub_probe()
1519 mutex_init(&sai->ctrl_lock); in stm32_sai_sub_probe()
1520 spin_lock_init(&sai->irq_lock); in stm32_sai_sub_probe()
1523 sai->pdata = dev_get_drvdata(pdev->dev.parent); in stm32_sai_sub_probe()
1524 if (!sai->pdata) { in stm32_sai_sub_probe()
1525 dev_err(&pdev->dev, "Parent device data not available\n"); in stm32_sai_sub_probe()
1526 return -EINVAL; in stm32_sai_sub_probe()
1534 sai->cpu_dai_drv = stm32_sai_playback_dai; in stm32_sai_sub_probe()
1536 sai->cpu_dai_drv = stm32_sai_capture_dai; in stm32_sai_sub_probe()
1537 sai->cpu_dai_drv.name = dev_name(&pdev->dev); in stm32_sai_sub_probe()
1539 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, in stm32_sai_sub_probe()
1540 IRQF_SHARED, dev_name(&pdev->dev), sai); in stm32_sai_sub_probe()
1542 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); in stm32_sai_sub_probe()
1549 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0); in stm32_sai_sub_probe()
1551 return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n"); in stm32_sai_sub_probe()
1553 ret = snd_soc_register_component(&pdev->dev, &stm32_component, in stm32_sai_sub_probe()
1554 &sai->cpu_dai_drv, 1); in stm32_sai_sub_probe()
1556 snd_dmaengine_pcm_unregister(&pdev->dev); in stm32_sai_sub_probe()
1560 pm_runtime_enable(&pdev->dev); in stm32_sai_sub_probe()
1567 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); in stm32_sai_sub_remove()
1569 clk_unprepare(sai->pdata->pclk); in stm32_sai_sub_remove()
1570 snd_dmaengine_pcm_unregister(&pdev->dev); in stm32_sai_sub_remove()
1571 snd_soc_unregister_component(&pdev->dev); in stm32_sai_sub_remove()
1572 pm_runtime_disable(&pdev->dev); in stm32_sai_sub_remove()
1581 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_suspend()
1585 regcache_cache_only(sai->regmap, true); in stm32_sai_sub_suspend()
1586 regcache_mark_dirty(sai->regmap); in stm32_sai_sub_suspend()
1588 clk_disable(sai->pdata->pclk); in stm32_sai_sub_suspend()
1598 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_resume()
1602 regcache_cache_only(sai->regmap, false); in stm32_sai_sub_resume()
1603 ret = regcache_sync(sai->regmap); in stm32_sai_sub_resume()
1605 clk_disable(sai->pdata->pclk); in stm32_sai_sub_resume()
1617 .name = "st,stm32-sai-sub",
1627 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1629 MODULE_ALIAS("platform:st,stm32-sai-sub");