Lines Matching +full:pdm +full:- +full:clk +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata))
68 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
70 * @regmap: SAI register map pointer
71 * @regmap_config: SAI sub block register map configuration pointer
82 * @id: SAI sub block id corresponding to sub-block A or B
89 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
113 struct clk *sai_ck;
114 struct clk *sai_mclk;
201 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_up()
205 ret = regmap_update_bits(sai->regmap, reg, mask, val); in stm32_sai_sub_reg_up()
207 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_up()
218 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_wr()
222 ret = regmap_write_bits(sai->regmap, reg, mask, val); in stm32_sai_sub_reg_wr()
224 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_wr()
234 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_rd()
238 ret = regmap_read(sai->regmap, reg, val); in stm32_sai_sub_reg_rd()
240 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_rd()
272 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in snd_pcm_iec958_info()
273 uinfo->count = 1; in snd_pcm_iec958_info()
283 mutex_lock(&sai->ctrl_lock); in snd_pcm_iec958_get()
284 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); in snd_pcm_iec958_get()
285 mutex_unlock(&sai->ctrl_lock); in snd_pcm_iec958_get()
295 mutex_lock(&sai->ctrl_lock); in snd_pcm_iec958_put()
296 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); in snd_pcm_iec958_put()
297 mutex_unlock(&sai->ctrl_lock); in snd_pcm_iec958_put()
325 int version = sai->pdata->conf.version; in stm32_sai_get_clk_div()
330 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); in stm32_sai_get_clk_div()
331 return -EINVAL; in stm32_sai_get_clk_div()
333 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); in stm32_sai_get_clk_div()
336 dev_dbg(&sai->pdev->dev, in stm32_sai_get_clk_div()
346 int version = sai->pdata->conf.version; in stm32_sai_set_clk_div()
350 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); in stm32_sai_set_clk_div()
351 return -EINVAL; in stm32_sai_set_clk_div()
358 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); in stm32_sai_set_clk_div()
372 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate))); in stm32_sai_rate_accurate()
384 struct platform_device *pdev = sai->pdev; in stm32_sai_set_parent_clk()
385 struct clk *parent_clk = sai->pdata->clk_x8k; in stm32_sai_set_parent_clk()
389 parent_clk = sai->pdata->clk_x11k; in stm32_sai_set_parent_clk()
391 ret = clk_set_parent(sai->sai_ck, parent_clk); in stm32_sai_set_parent_clk()
393 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", in stm32_sai_set_parent_clk()
394 ret, ret == -EBUSY ? in stm32_sai_set_parent_clk()
402 if (sai->sai_ck_used) { in stm32_sai_put_parent_rate()
403 sai->sai_ck_used = false; in stm32_sai_put_parent_rate()
404 clk_rate_exclusive_put(sai->sai_ck); in stm32_sai_put_parent_rate()
411 struct platform_device *pdev = sai->pdev; in stm32_sai_set_parent_rate()
417 * - mclk on or spdif: in stm32_sai_set_parent_rate()
418 * f_sai_ck = MCKDIV * mclk-fs * fs in stm32_sai_set_parent_rate()
419 * Here typical 256 ratio is assumed for mclk-fs in stm32_sai_set_parent_rate()
420 * - mclk off: in stm32_sai_set_parent_rate()
432 if (!sai->sai_mclk && !STM_SAI_PROTOCOL_IS_SPDIF(sai)) { in stm32_sai_set_parent_rate()
433 sai_ck_min_rate = rate * sai->fs_length; in stm32_sai_set_parent_rate()
434 sai_ck_max_rate /= DIV_ROUND_CLOSEST(256, roundup_pow_of_two(sai->fs_length)); in stm32_sai_set_parent_rate()
438 * Request exclusivity, as the clock is shared by SAI sub-blocks and by in stm32_sai_set_parent_rate()
442 clk_rate_exclusive_get(sai->sai_ck); in stm32_sai_set_parent_rate()
443 sai->sai_ck_used = true; in stm32_sai_set_parent_rate()
449 sai_curr_rate = clk_get_rate(sai->sai_ck); in stm32_sai_set_parent_rate()
450 dev_dbg(&pdev->dev, "kernel clock rate: min [%u], max [%u], current [%u]", in stm32_sai_set_parent_rate()
465 sai_new_rate = clk_round_rate(sai->sai_ck, sai_ck_rate); in stm32_sai_set_parent_rate()
467 ret = clk_set_rate(sai->sai_ck, sai_ck_rate); in stm32_sai_set_parent_rate()
469 dev_err(&pdev->dev, "Error %d setting sai_ck rate. %s", in stm32_sai_set_parent_rate()
470 ret, ret == -EBUSY ? in stm32_sai_set_parent_rate()
484 dev_err(&pdev->dev, "Failed to find an accurate rate"); in stm32_sai_set_parent_rate()
489 return -EINVAL; in stm32_sai_set_parent_rate()
496 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_determine_rate()
499 div = stm32_sai_get_clk_div(sai, req->best_parent_rate, req->rate); in stm32_sai_mclk_determine_rate()
501 return -EINVAL; in stm32_sai_mclk_determine_rate()
503 mclk->freq = req->best_parent_rate / div; in stm32_sai_mclk_determine_rate()
505 req->rate = mclk->freq; in stm32_sai_mclk_determine_rate()
515 return mclk->freq; in stm32_sai_mclk_recalc_rate()
522 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_set_rate()
533 mclk->freq = rate; in stm32_sai_mclk_set_rate()
541 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_enable()
543 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); in stm32_sai_mclk_enable()
552 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_disable()
554 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); in stm32_sai_mclk_disable()
571 struct device *dev = &sai->pdev->dev; in stm32_sai_add_mclk_provider()
572 const char *pname = __clk_get_name(sai->sai_ck); in stm32_sai_add_mclk_provider()
578 return -ENOMEM; in stm32_sai_add_mclk_provider()
583 return -ENOMEM; in stm32_sai_add_mclk_provider()
590 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { in stm32_sai_add_mclk_provider()
596 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); in stm32_sai_add_mclk_provider()
597 mclk->sai_data = sai; in stm32_sai_add_mclk_provider()
598 hw = &mclk->hw; in stm32_sai_add_mclk_provider()
601 ret = devm_clk_hw_register(&sai->pdev->dev, hw); in stm32_sai_add_mclk_provider()
606 sai->sai_mclk = hw->clk; in stm32_sai_add_mclk_provider()
615 struct platform_device *pdev = sai->pdev; in stm32_sai_isr()
629 if (!sai->substream) { in stm32_sai_isr()
630 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); in stm32_sai_isr()
635 dev_err(&pdev->dev, "IRQ %s\n", in stm32_sai_isr()
641 dev_dbg(&pdev->dev, "IRQ mute detected\n"); in stm32_sai_isr()
644 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); in stm32_sai_isr()
649 dev_err(&pdev->dev, "IRQ Codec not ready\n"); in stm32_sai_isr()
652 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); in stm32_sai_isr()
657 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); in stm32_sai_isr()
661 spin_lock(&sai->irq_lock); in stm32_sai_isr()
662 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) in stm32_sai_isr()
663 snd_pcm_stop_xrun(sai->substream); in stm32_sai_isr()
664 spin_unlock(&sai->irq_lock); in stm32_sai_isr()
675 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { in stm32_sai_set_sysclk()
685 if (sai->mclk_rate) { in stm32_sai_set_sysclk()
686 clk_rate_exclusive_put(sai->sai_mclk); in stm32_sai_set_sysclk()
687 sai->mclk_rate = 0; in stm32_sai_set_sysclk()
690 if (sai->put_sai_ck_rate) in stm32_sai_set_sysclk()
691 sai->put_sai_ck_rate(sai); in stm32_sai_set_sysclk()
697 ret = sai->set_sai_ck_rate(sai, freq); in stm32_sai_set_sysclk()
701 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); in stm32_sai_set_sysclk()
703 dev_err(cpu_dai->dev, in stm32_sai_set_sysclk()
704 ret == -EBUSY ? in stm32_sai_set_sysclk()
710 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); in stm32_sai_set_sysclk()
711 sai->mclk_rate = freq; in stm32_sai_set_sysclk()
724 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); in stm32_sai_set_dai_tdm_slot()
728 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", in stm32_sai_set_dai_tdm_slot()
744 SAI_XSLOTR_NBSLOT_SET(slots - 1); in stm32_sai_set_dai_tdm_slot()
749 sai->slot_mask = tx_mask; in stm32_sai_set_dai_tdm_slot()
754 sai->slot_mask = rx_mask; in stm32_sai_set_dai_tdm_slot()
762 sai->slot_width = slot_width; in stm32_sai_set_dai_tdm_slot()
763 sai->slots = slots; in stm32_sai_set_dai_tdm_slot()
775 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); in stm32_sai_set_dai_fmt()
810 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", in stm32_sai_set_dai_fmt()
812 return -EINVAL; in stm32_sai_set_dai_fmt()
835 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", in stm32_sai_set_dai_fmt()
837 return -EINVAL; in stm32_sai_set_dai_fmt()
849 sai->master = false; in stm32_sai_set_dai_fmt()
852 sai->master = true; in stm32_sai_set_dai_fmt()
855 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", in stm32_sai_set_dai_fmt()
857 return -EINVAL; in stm32_sai_set_dai_fmt()
860 /* Set slave mode if sub-block is synchronized with another SAI */ in stm32_sai_set_dai_fmt()
861 if (sai->sync) { in stm32_sai_set_dai_fmt()
862 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); in stm32_sai_set_dai_fmt()
864 sai->master = false; in stm32_sai_set_dai_fmt()
872 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_set_dai_fmt()
876 sai->fmt = fmt; in stm32_sai_set_dai_fmt()
888 spin_lock_irqsave(&sai->irq_lock, flags); in stm32_sai_startup()
889 sai->substream = substream; in stm32_sai_startup()
890 spin_unlock_irqrestore(&sai->irq_lock, flags); in stm32_sai_startup()
893 snd_pcm_hw_constraint_mask64(substream->runtime, in stm32_sai_startup()
896 snd_pcm_hw_constraint_single(substream->runtime, in stm32_sai_startup()
900 ret = clk_prepare_enable(sai->sai_ck); in stm32_sai_startup()
902 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); in stm32_sai_startup()
917 if (sai->master) in stm32_sai_startup()
947 sai->spdif_frm_cnt = 0; in stm32_sai_set_config()
964 dev_err(cpu_dai->dev, "Data format not supported\n"); in stm32_sai_set_config()
965 return -EINVAL; in stm32_sai_set_config()
969 if ((sai->slots == 2) && (params_channels(params) == 1)) in stm32_sai_set_config()
974 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_set_config()
994 sai->slot_width = sai->data_size; in stm32_sai_set_slots()
996 if (sai->slot_width < sai->data_size) { in stm32_sai_set_slots()
997 dev_err(cpu_dai->dev, in stm32_sai_set_slots()
999 sai->data_size); in stm32_sai_set_slots()
1000 return -EINVAL; in stm32_sai_set_slots()
1004 if (!sai->slots) in stm32_sai_set_slots()
1005 sai->slots = 2; in stm32_sai_set_slots()
1010 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); in stm32_sai_set_slots()
1014 sai->slot_mask = (1 << sai->slots) - 1; in stm32_sai_set_slots()
1017 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); in stm32_sai_set_slots()
1020 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", in stm32_sai_set_slots()
1021 sai->slots, sai->slot_width); in stm32_sai_set_slots()
1032 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; in stm32_sai_set_frame()
1033 sai->fs_length = sai->slot_width * sai->slots; in stm32_sai_set_frame()
1035 fs_active = sai->fs_length / 2; in stm32_sai_set_frame()
1040 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); in stm32_sai_set_frame()
1041 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); in stm32_sai_set_frame()
1044 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", in stm32_sai_set_frame()
1045 sai->fs_length, fs_active); in stm32_sai_set_frame()
1049 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { in stm32_sai_set_frame()
1050 offset = sai->slot_width - sai->data_size; in stm32_sai_set_frame()
1060 unsigned char *cs = sai->iec958.status; in stm32_sai_init_iec958_status()
1075 mutex_lock(&sai->ctrl_lock); in stm32_sai_set_iec958_status()
1076 switch (runtime->rate) { in stm32_sai_set_iec958_status()
1078 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; in stm32_sai_set_iec958_status()
1081 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; in stm32_sai_set_iec958_status()
1084 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; in stm32_sai_set_iec958_status()
1087 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; in stm32_sai_set_iec958_status()
1090 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; in stm32_sai_set_iec958_status()
1093 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; in stm32_sai_set_iec958_status()
1096 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; in stm32_sai_set_iec958_status()
1099 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; in stm32_sai_set_iec958_status()
1102 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; in stm32_sai_set_iec958_status()
1105 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; in stm32_sai_set_iec958_status()
1108 mutex_unlock(&sai->ctrl_lock); in stm32_sai_set_iec958_status()
1120 if (!sai->sai_mclk) { in stm32_sai_configure_clock()
1121 ret = sai->set_sai_ck_rate(sai, rate); in stm32_sai_configure_clock()
1125 sai_clk_rate = clk_get_rate(sai->sai_ck); in stm32_sai_configure_clock()
1127 if (STM_SAI_IS_F4(sai->pdata)) { in stm32_sai_configure_clock()
1135 if (!sai->mclk_rate) in stm32_sai_configure_clock()
1138 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { in stm32_sai_configure_clock()
1140 2 * sai->mclk_rate); in stm32_sai_configure_clock()
1160 if (sai->mclk_rate) { in stm32_sai_configure_clock()
1161 mclk_ratio = sai->mclk_rate / rate; in stm32_sai_configure_clock()
1165 dev_err(cpu_dai->dev, in stm32_sai_configure_clock()
1168 return -EINVAL; in stm32_sai_configure_clock()
1176 sai->mclk_rate); in stm32_sai_configure_clock()
1180 /* mclk-fs not set, master clock not active */ in stm32_sai_configure_clock()
1181 den = sai->fs_length * params_rate(params); in stm32_sai_configure_clock()
1200 sai->data_size = params_width(params); in stm32_sai_hw_params()
1204 substream->runtime->rate = params_rate(params); in stm32_sai_hw_params()
1205 stm32_sai_set_iec958_status(sai, substream->runtime); in stm32_sai_hw_params()
1217 if (sai->master) in stm32_sai_hw_params()
1233 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); in stm32_sai_trigger()
1242 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_trigger()
1247 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); in stm32_sai_trigger()
1260 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_trigger()
1263 sai->spdif_frm_cnt = 0; in stm32_sai_trigger()
1266 return -EINVAL; in stm32_sai_trigger()
1280 clk_disable_unprepare(sai->sai_ck); in stm32_sai_shutdown()
1284 * - Master clock is not used. Kernel clock won't be released trough sysclk in stm32_sai_shutdown()
1285 * - Put handler is defined. Involve that clock is managed exclusively in stm32_sai_shutdown()
1287 if (!sai->sai_mclk && sai->put_sai_ck_rate) in stm32_sai_shutdown()
1288 sai->put_sai_ck_rate(sai); in stm32_sai_shutdown()
1290 spin_lock_irqsave(&sai->irq_lock, flags); in stm32_sai_shutdown()
1291 sai->substream = NULL; in stm32_sai_shutdown()
1292 spin_unlock_irqrestore(&sai->irq_lock, flags); in stm32_sai_shutdown()
1298 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_pcm_new()
1302 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); in stm32_sai_pcm_new()
1303 knew.device = rtd->pcm->device; in stm32_sai_pcm_new()
1304 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); in stm32_sai_pcm_new()
1312 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_dai_probe()
1315 sai->cpu_dai = cpu_dai; in stm32_sai_dai_probe()
1317 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); in stm32_sai_dai_probe()
1320 * as it allows bytes, half-word and words transfers. (See DMA fifos in stm32_sai_dai_probe()
1323 sai->dma_params.maxburst = 4; in stm32_sai_dai_probe()
1324 if (sai->pdata->conf.fifo_size < 8 || sai->pdata->conf.no_dma_burst) in stm32_sai_dai_probe()
1325 sai->dma_params.maxburst = 1; in stm32_sai_dai_probe()
1327 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; in stm32_sai_dai_probe()
1330 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); in stm32_sai_dai_probe()
1332 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); in stm32_sai_dai_probe()
1343 if (sai->sync == SAI_SYNC_EXTERNAL) { in stm32_sai_dai_probe()
1345 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, in stm32_sai_dai_probe()
1346 sai->synco, sai->synci); in stm32_sai_dai_probe()
1352 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); in stm32_sai_dai_probe()
1384 struct snd_pcm_runtime *runtime = substream->runtime; in stm32_sai_pcm_process_spdif()
1387 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_pcm_process_spdif()
1388 int *ptr = (int *)(runtime->dma_area + hwoff + in stm32_sai_pcm_process_spdif()
1389 channel * (runtime->dma_bytes / runtime->channels)); in stm32_sai_pcm_process_spdif()
1391 unsigned int frm_cnt = sai->spdif_frm_cnt; in stm32_sai_pcm_process_spdif()
1400 mask = 1 << (frm_cnt - (byte << 3)); in stm32_sai_pcm_process_spdif()
1401 if (sai->iec958.status[byte] & mask) in stm32_sai_pcm_process_spdif()
1410 } while (--cnt); in stm32_sai_pcm_process_spdif()
1411 sai->spdif_frm_cnt = frm_cnt; in stm32_sai_pcm_process_spdif()
1481 .name = "stm32-sai",
1486 { .compatible = "st,stm32-sai-sub-a",
1488 { .compatible = "st,stm32-sai-sub-b",
1497 struct device_node *np = pdev->dev.of_node; in stm32_sai_sub_parse_of()
1504 return -ENODEV; in stm32_sai_sub_parse_of()
1510 sai->phys_addr = res->start; in stm32_sai_sub_parse_of()
1512 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; in stm32_sai_sub_parse_of()
1513 /* Note: PDM registers not available for sub-block B */ in stm32_sai_sub_parse_of()
1515 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; in stm32_sai_sub_parse_of()
1522 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, in stm32_sai_sub_parse_of()
1523 sai->regmap_config); in stm32_sai_sub_parse_of()
1524 if (IS_ERR(sai->regmap)) in stm32_sai_sub_parse_of()
1525 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap), in stm32_sai_sub_parse_of()
1529 if (of_property_match_string(np, "dma-names", "tx") >= 0) { in stm32_sai_sub_parse_of()
1530 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; in stm32_sai_sub_parse_of()
1531 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { in stm32_sai_sub_parse_of()
1532 sai->dir = SNDRV_PCM_STREAM_CAPTURE; in stm32_sai_sub_parse_of()
1534 dev_err(&pdev->dev, "Unsupported direction\n"); in stm32_sai_sub_parse_of()
1535 return -EINVAL; in stm32_sai_sub_parse_of()
1539 sai->spdif = false; in stm32_sai_sub_parse_of()
1542 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { in stm32_sai_sub_parse_of()
1543 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); in stm32_sai_sub_parse_of()
1544 return -EINVAL; in stm32_sai_sub_parse_of()
1547 sai->spdif = true; in stm32_sai_sub_parse_of()
1548 sai->master = true; in stm32_sai_sub_parse_of()
1554 if (ret < 0 && ret != -ENOENT) { in stm32_sai_sub_parse_of()
1555 dev_err(&pdev->dev, "Failed to get st,sync property\n"); in stm32_sai_sub_parse_of()
1559 sai->sync = SAI_SYNC_NONE; in stm32_sai_sub_parse_of()
1562 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); in stm32_sai_sub_parse_of()
1564 return -EINVAL; in stm32_sai_sub_parse_of()
1567 sai->np_sync_provider = of_get_parent(args.np); in stm32_sai_sub_parse_of()
1568 if (!sai->np_sync_provider) { in stm32_sai_sub_parse_of()
1569 dev_err(&pdev->dev, "%pOFn parent node not found\n", in stm32_sai_sub_parse_of()
1572 return -ENODEV; in stm32_sai_sub_parse_of()
1575 sai->sync = SAI_SYNC_INTERNAL; in stm32_sai_sub_parse_of()
1576 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { in stm32_sai_sub_parse_of()
1578 dev_err(&pdev->dev, in stm32_sai_sub_parse_of()
1581 return -EINVAL; in stm32_sai_sub_parse_of()
1583 sai->sync = SAI_SYNC_EXTERNAL; in stm32_sai_sub_parse_of()
1585 sai->synci = args.args[0]; in stm32_sai_sub_parse_of()
1586 if (sai->synci < 1 || in stm32_sai_sub_parse_of()
1587 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { in stm32_sai_sub_parse_of()
1588 dev_err(&pdev->dev, "Wrong SAI index\n"); in stm32_sai_sub_parse_of()
1590 return -EINVAL; in stm32_sai_sub_parse_of()
1594 "st,stm32-sai-sub-a") >= 0) in stm32_sai_sub_parse_of()
1595 sai->synco = STM_SAI_SYNC_OUT_A; in stm32_sai_sub_parse_of()
1598 "st,stm32-sai-sub-b") >= 0) in stm32_sai_sub_parse_of()
1599 sai->synco = STM_SAI_SYNC_OUT_B; in stm32_sai_sub_parse_of()
1601 if (!sai->synco) { in stm32_sai_sub_parse_of()
1602 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); in stm32_sai_sub_parse_of()
1604 return -EINVAL; in stm32_sai_sub_parse_of()
1608 dev_dbg(&pdev->dev, "%s synchronized with %s\n", in stm32_sai_sub_parse_of()
1609 pdev->name, args.np->full_name); in stm32_sai_sub_parse_of()
1613 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); in stm32_sai_sub_parse_of()
1614 if (IS_ERR(sai->sai_ck)) in stm32_sai_sub_parse_of()
1615 return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck), in stm32_sai_sub_parse_of()
1618 ret = clk_prepare(sai->pdata->pclk); in stm32_sai_sub_parse_of()
1622 if (STM_SAI_IS_F4(sai->pdata)) in stm32_sai_sub_parse_of()
1626 if (of_property_present(np, "#clock-cells")) { in stm32_sai_sub_parse_of()
1631 sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK"); in stm32_sai_sub_parse_of()
1632 if (IS_ERR(sai->sai_mclk)) in stm32_sai_sub_parse_of()
1633 return PTR_ERR(sai->sai_mclk); in stm32_sai_sub_parse_of()
1645 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); in stm32_sai_sub_probe()
1647 return -ENOMEM; in stm32_sai_sub_probe()
1649 sai->id = (uintptr_t)device_get_match_data(&pdev->dev); in stm32_sai_sub_probe()
1651 sai->pdev = pdev; in stm32_sai_sub_probe()
1652 mutex_init(&sai->ctrl_lock); in stm32_sai_sub_probe()
1653 spin_lock_init(&sai->irq_lock); in stm32_sai_sub_probe()
1656 sai->pdata = dev_get_drvdata(pdev->dev.parent); in stm32_sai_sub_probe()
1657 if (!sai->pdata) { in stm32_sai_sub_probe()
1658 dev_err(&pdev->dev, "Parent device data not available\n"); in stm32_sai_sub_probe()
1659 return -EINVAL; in stm32_sai_sub_probe()
1662 if (sai->pdata->conf.get_sai_ck_parent) { in stm32_sai_sub_probe()
1663 sai->set_sai_ck_rate = stm32_sai_set_parent_clk; in stm32_sai_sub_probe()
1665 sai->set_sai_ck_rate = stm32_sai_set_parent_rate; in stm32_sai_sub_probe()
1666 sai->put_sai_ck_rate = stm32_sai_put_parent_rate; in stm32_sai_sub_probe()
1674 sai->cpu_dai_drv = stm32_sai_playback_dai; in stm32_sai_sub_probe()
1676 sai->cpu_dai_drv = stm32_sai_capture_dai; in stm32_sai_sub_probe()
1677 sai->cpu_dai_drv.name = dev_name(&pdev->dev); in stm32_sai_sub_probe()
1679 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, in stm32_sai_sub_probe()
1680 IRQF_SHARED, dev_name(&pdev->dev), sai); in stm32_sai_sub_probe()
1682 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); in stm32_sai_sub_probe()
1689 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0); in stm32_sai_sub_probe()
1691 return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n"); in stm32_sai_sub_probe()
1693 ret = snd_soc_register_component(&pdev->dev, &stm32_component, in stm32_sai_sub_probe()
1694 &sai->cpu_dai_drv, 1); in stm32_sai_sub_probe()
1696 snd_dmaengine_pcm_unregister(&pdev->dev); in stm32_sai_sub_probe()
1700 pm_runtime_enable(&pdev->dev); in stm32_sai_sub_probe()
1707 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); in stm32_sai_sub_remove()
1709 clk_unprepare(sai->pdata->pclk); in stm32_sai_sub_remove()
1710 snd_dmaengine_pcm_unregister(&pdev->dev); in stm32_sai_sub_remove()
1711 snd_soc_unregister_component(&pdev->dev); in stm32_sai_sub_remove()
1712 pm_runtime_disable(&pdev->dev); in stm32_sai_sub_remove()
1720 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_suspend()
1724 regcache_cache_only(sai->regmap, true); in stm32_sai_sub_suspend()
1725 regcache_mark_dirty(sai->regmap); in stm32_sai_sub_suspend()
1727 clk_disable(sai->pdata->pclk); in stm32_sai_sub_suspend()
1737 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_resume()
1741 regcache_cache_only(sai->regmap, false); in stm32_sai_sub_resume()
1742 ret = regcache_sync(sai->regmap); in stm32_sai_sub_resume()
1744 clk_disable(sai->pdata->pclk); in stm32_sai_sub_resume()
1755 .name = "st,stm32-sai-sub",
1765 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1767 MODULE_ALIAS("platform:st,stm32-sai-sub");