Lines Matching +full:stm32h7 +full:- +full:spi
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
208 * struct stm32_i2s_data - private data of I2S
266 * struct stm32_i2s_conf - I2S configuration
303 dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n", in stm32_i2s_calc_clk_div()
309 dev_err(&i2s->pdev->dev, "Wrong divider setting\n"); in stm32_i2s_calc_clk_div()
310 return -EINVAL; in stm32_i2s_calc_clk_div()
314 dev_dbg(&i2s->pdev->dev, in stm32_i2s_calc_clk_div()
318 i2s->div = div; in stm32_i2s_calc_clk_div()
319 i2s->odd = odd; in stm32_i2s_calc_clk_div()
320 i2s->divider = divider; in stm32_i2s_calc_clk_div()
329 cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT); in stm32_i2s_set_clk_div()
332 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, in stm32_i2s_set_clk_div()
339 struct platform_device *pdev = i2s->pdev; in stm32_i2s_rate_accurate()
344 dev_err(&pdev->dev, "Unexpected null rate\n"); in stm32_i2s_rate_accurate()
352 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate))); in stm32_i2s_rate_accurate()
358 dev_dbg(&pdev->dev, "Rate [%u] not accurate\n", rate); in stm32_i2s_rate_accurate()
366 struct platform_device *pdev = i2s->pdev; in stm32_i2s_set_parent_clock()
371 parent_clk = i2s->x11kclk; in stm32_i2s_set_parent_clock()
373 parent_clk = i2s->x8kclk; in stm32_i2s_set_parent_clock()
375 ret = clk_set_parent(i2s->i2sclk, parent_clk); in stm32_i2s_set_parent_clock()
377 dev_err(&pdev->dev, in stm32_i2s_set_parent_clock()
385 if (i2s->i2s_clk_flg) { in stm32_i2s_put_parent_rate()
386 i2s->i2s_clk_flg = false; in stm32_i2s_put_parent_rate()
387 clk_rate_exclusive_put(i2s->i2sclk); in stm32_i2s_put_parent_rate()
394 struct platform_device *pdev = i2s->pdev; in stm32_i2s_set_parent_rate()
400 * - mclk on: in stm32_i2s_set_parent_rate()
401 * f_i2s_ck = MCKDIV * mclk-fs * fs in stm32_i2s_set_parent_rate()
402 * Here typical 256 ratio is assumed for mclk-fs in stm32_i2s_set_parent_rate()
403 * - mclk off: in stm32_i2s_set_parent_rate()
413 if (!i2s->i2smclk) in stm32_i2s_set_parent_rate()
417 clk_rate_exclusive_get(i2s->i2sclk); in stm32_i2s_set_parent_rate()
418 i2s->i2s_clk_flg = true; in stm32_i2s_set_parent_rate()
424 i2s_curr_rate = clk_get_rate(i2s->i2sclk); in stm32_i2s_set_parent_rate()
437 i2s_new_rate = clk_round_rate(i2s->i2sclk, i2s_clk_rate); in stm32_i2s_set_parent_rate()
439 ret = clk_set_rate(i2s->i2sclk, i2s_clk_rate); in stm32_i2s_set_parent_rate()
441 dev_err(&pdev->dev, "Error %d setting i2s_clk_rate rate. %s", in stm32_i2s_set_parent_rate()
442 ret, ret == -EBUSY ? in stm32_i2s_set_parent_rate()
456 dev_err(&pdev->dev, "Failed to find an accurate rate"); in stm32_i2s_set_parent_rate()
461 return -EINVAL; in stm32_i2s_set_parent_rate()
468 struct stm32_i2s_data *i2s = mclk->i2s_data; in stm32_i2smclk_round_rate()
475 mclk->freq = *prate / i2s->divider; in stm32_i2smclk_round_rate()
477 return mclk->freq; in stm32_i2smclk_round_rate()
485 return mclk->freq; in stm32_i2smclk_recalc_rate()
492 struct stm32_i2s_data *i2s = mclk->i2s_data; in stm32_i2smclk_set_rate()
503 mclk->freq = rate; in stm32_i2smclk_set_rate()
511 struct stm32_i2s_data *i2s = mclk->i2s_data; in stm32_i2smclk_enable()
513 dev_dbg(&i2s->pdev->dev, "Enable master clock\n"); in stm32_i2smclk_enable()
515 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, in stm32_i2smclk_enable()
522 struct stm32_i2s_data *i2s = mclk->i2s_data; in stm32_i2smclk_disable()
524 dev_dbg(&i2s->pdev->dev, "Disable master clock\n"); in stm32_i2smclk_disable()
526 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0); in stm32_i2smclk_disable()
541 struct device *dev = &i2s->pdev->dev; in stm32_i2s_add_mclk_provider()
542 const char *pname = __clk_get_name(i2s->i2sclk); in stm32_i2s_add_mclk_provider()
548 return -ENOMEM; in stm32_i2s_add_mclk_provider()
553 return -ENOMEM; in stm32_i2s_add_mclk_provider()
560 while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) { in stm32_i2s_add_mclk_provider()
566 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); in stm32_i2s_add_mclk_provider()
567 mclk->i2s_data = i2s; in stm32_i2s_add_mclk_provider()
568 hw = &mclk->hw; in stm32_i2s_add_mclk_provider()
571 ret = devm_clk_hw_register(&i2s->pdev->dev, hw); in stm32_i2s_add_mclk_provider()
576 i2s->i2smclk = hw->clk; in stm32_i2s_add_mclk_provider()
585 struct platform_device *pdev = i2s->pdev; in stm32_i2s_isr()
590 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr); in stm32_i2s_isr()
591 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier); in stm32_i2s_isr()
595 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n", in stm32_i2s_isr()
600 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, in stm32_i2s_isr()
604 dev_dbg(&pdev->dev, "Overrun\n"); in stm32_i2s_isr()
609 dev_dbg(&pdev->dev, "Underrun\n"); in stm32_i2s_isr()
614 dev_dbg(&pdev->dev, "Frame error\n"); in stm32_i2s_isr()
616 spin_lock(&i2s->irq_lock); in stm32_i2s_isr()
617 if (err && i2s->substream) in stm32_i2s_isr()
618 snd_pcm_stop_xrun(i2s->substream); in stm32_i2s_isr()
619 spin_unlock(&i2s->irq_lock); in stm32_i2s_isr()
678 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); in stm32_i2s_set_dai_fmt()
699 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", in stm32_i2s_set_dai_fmt()
701 return -EINVAL; in stm32_i2s_set_dai_fmt()
719 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", in stm32_i2s_set_dai_fmt()
721 return -EINVAL; in stm32_i2s_set_dai_fmt()
727 i2s->ms_flg = I2S_MS_SLAVE; in stm32_i2s_set_dai_fmt()
730 i2s->ms_flg = I2S_MS_MASTER; in stm32_i2s_set_dai_fmt()
733 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", in stm32_i2s_set_dai_fmt()
735 return -EINVAL; in stm32_i2s_set_dai_fmt()
738 i2s->fmt = fmt; in stm32_i2s_set_dai_fmt()
739 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, in stm32_i2s_set_dai_fmt()
749 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n", in stm32_i2s_set_sysclk()
755 if (!i2s->i2smclk) { in stm32_i2s_set_sysclk()
756 dev_dbg(cpu_dai->dev, "No MCLK registered\n"); in stm32_i2s_set_sysclk()
763 if (i2s->mclk_rate) { in stm32_i2s_set_sysclk()
764 clk_rate_exclusive_put(i2s->i2smclk); in stm32_i2s_set_sysclk()
765 i2s->mclk_rate = 0; in stm32_i2s_set_sysclk()
768 if (i2s->put_i2s_clk_rate) in stm32_i2s_set_sysclk()
769 i2s->put_i2s_clk_rate(i2s); in stm32_i2s_set_sysclk()
771 return regmap_update_bits(i2s->regmap, in stm32_i2s_set_sysclk()
776 ret = i2s->set_i2s_clk_rate(i2s, freq); in stm32_i2s_set_sysclk()
779 ret = clk_set_rate_exclusive(i2s->i2smclk, freq); in stm32_i2s_set_sysclk()
781 dev_err(cpu_dai->dev, "Could not set mclk rate\n"); in stm32_i2s_set_sysclk()
784 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, in stm32_i2s_set_sysclk()
787 i2s->mclk_rate = freq; in stm32_i2s_set_sysclk()
803 if (!i2s->mclk_rate) { in stm32_i2s_configure_clock()
804 ret = i2s->set_i2s_clk_rate(i2s, rate); in stm32_i2s_configure_clock()
808 i2s_clock_rate = clk_get_rate(i2s->i2sclk); in stm32_i2s_configure_clock()
822 if (i2s->mclk_rate) { in stm32_i2s_configure_clock()
824 i2s->mclk_rate); in stm32_i2s_configure_clock()
829 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == in stm32_i2s_configure_clock()
834 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr); in stm32_i2s_configure_clock()
850 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG, in stm32_i2s_configure_clock()
875 dev_err(cpu_dai->dev, "Unexpected format %d", format); in stm32_i2s_configure()
876 return -EINVAL; in stm32_i2s_configure()
890 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, in stm32_i2s_configure()
896 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1); in stm32_i2s_configure()
898 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, in stm32_i2s_configure()
909 spin_lock_irqsave(&i2s->irq_lock, flags); in stm32_i2s_startup()
910 i2s->substream = substream; in stm32_i2s_startup()
911 spin_unlock_irqrestore(&i2s->irq_lock, flags); in stm32_i2s_startup()
913 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A) in stm32_i2s_startup()
914 snd_pcm_hw_constraint_single(substream->runtime, in stm32_i2s_startup()
917 ret = clk_prepare_enable(i2s->i2sclk); in stm32_i2s_startup()
919 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); in stm32_i2s_startup()
923 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, in stm32_i2s_startup()
936 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret); in stm32_i2s_hw_params()
950 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in stm32_i2s_trigger()
959 dev_dbg(cpu_dai->dev, "start I2S %s\n", in stm32_i2s_trigger()
960 snd_pcm_direction_name(substream->stream)); in stm32_i2s_trigger()
963 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, in stm32_i2s_trigger()
966 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG, in stm32_i2s_trigger()
969 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret); in stm32_i2s_trigger()
973 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG, in stm32_i2s_trigger()
976 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret); in stm32_i2s_trigger()
980 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, in stm32_i2s_trigger()
983 spin_lock(&i2s->lock_fd); in stm32_i2s_trigger()
984 i2s->refcount++; in stm32_i2s_trigger()
990 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1) in stm32_i2s_trigger()
992 regmap_write(i2s->regmap, in stm32_i2s_trigger()
995 spin_unlock(&i2s->lock_fd); in stm32_i2s_trigger()
1000 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier); in stm32_i2s_trigger()
1005 dev_dbg(cpu_dai->dev, "stop I2S %s\n", in stm32_i2s_trigger()
1006 snd_pcm_direction_name(substream->stream)); in stm32_i2s_trigger()
1009 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, in stm32_i2s_trigger()
1013 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, in stm32_i2s_trigger()
1017 spin_lock(&i2s->lock_fd); in stm32_i2s_trigger()
1018 i2s->refcount--; in stm32_i2s_trigger()
1019 if (i2s->refcount) { in stm32_i2s_trigger()
1020 spin_unlock(&i2s->lock_fd); in stm32_i2s_trigger()
1024 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG, in stm32_i2s_trigger()
1027 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret); in stm32_i2s_trigger()
1028 spin_unlock(&i2s->lock_fd); in stm32_i2s_trigger()
1031 spin_unlock(&i2s->lock_fd); in stm32_i2s_trigger()
1034 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, in stm32_i2s_trigger()
1038 return -EINVAL; in stm32_i2s_trigger()
1050 clk_disable_unprepare(i2s->i2sclk); in stm32_i2s_shutdown()
1054 * - Master clock is not used. Kernel clock won't be released trough sysclk in stm32_i2s_shutdown()
1055 * - Put handler is defined. Involve that clock is managed exclusively in stm32_i2s_shutdown()
1057 if (!i2s->i2smclk && i2s->put_i2s_clk_rate) in stm32_i2s_shutdown()
1058 i2s->put_i2s_clk_rate(i2s); in stm32_i2s_shutdown()
1060 spin_lock_irqsave(&i2s->irq_lock, flags); in stm32_i2s_shutdown()
1061 i2s->substream = NULL; in stm32_i2s_shutdown()
1062 spin_unlock_irqrestore(&i2s->irq_lock, flags); in stm32_i2s_shutdown()
1067 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev); in stm32_i2s_dai_probe()
1068 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx; in stm32_i2s_dai_probe()
1069 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx; in stm32_i2s_dai_probe()
1072 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; in stm32_i2s_dai_probe()
1073 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG; in stm32_i2s_dai_probe()
1074 dma_data_tx->maxburst = 1; in stm32_i2s_dai_probe()
1075 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; in stm32_i2s_dai_probe()
1076 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG; in stm32_i2s_dai_probe()
1077 dma_data_rx->maxburst = 1; in stm32_i2s_dai_probe()
1123 .name = "stm32-i2s",
1130 stream->stream_name = stream_name; in stm32_i2s_dai_init()
1131 stream->channels_min = 1; in stm32_i2s_dai_init()
1132 stream->channels_max = 2; in stm32_i2s_dai_init()
1133 stream->rates = SNDRV_PCM_RATE_8000_192000; in stm32_i2s_dai_init()
1134 stream->formats = SNDRV_PCM_FMTBIT_S16_LE | in stm32_i2s_dai_init()
1143 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver), in stm32_i2s_dais_init()
1146 return -ENOMEM; in stm32_i2s_dais_init()
1148 dai_ptr->ops = &stm32_i2s_pcm_dai_ops; in stm32_i2s_dais_init()
1149 dai_ptr->id = 1; in stm32_i2s_dais_init()
1150 stm32_i2s_dai_init(&dai_ptr->playback, "playback"); in stm32_i2s_dais_init()
1151 stm32_i2s_dai_init(&dai_ptr->capture, "capture"); in stm32_i2s_dais_init()
1152 i2s->dai_drv = dai_ptr; in stm32_i2s_dais_init()
1167 { .compatible = "st,stm32h7-i2s", .data = &stm32_i2s_conf_h7 },
1168 { .compatible = "st,stm32mp25-i2s", .data = &stm32_i2s_conf_mp25 },
1174 struct device *dev = &i2s->pdev->dev; in stm32_i2s_get_parent_clk()
1176 i2s->x8kclk = devm_clk_get(dev, "x8k"); in stm32_i2s_get_parent_clk()
1177 if (IS_ERR(i2s->x8kclk)) in stm32_i2s_get_parent_clk()
1178 return dev_err_probe(dev, PTR_ERR(i2s->x8kclk), "Cannot get x8k parent clock\n"); in stm32_i2s_get_parent_clk()
1180 i2s->x11kclk = devm_clk_get(dev, "x11k"); in stm32_i2s_get_parent_clk()
1181 if (IS_ERR(i2s->x11kclk)) in stm32_i2s_get_parent_clk()
1182 return dev_err_probe(dev, PTR_ERR(i2s->x11kclk), "Cannot get x11k parent clock\n"); in stm32_i2s_get_parent_clk()
1190 struct device_node *np = pdev->dev.of_node; in stm32_i2s_parse_dt()
1196 return -ENODEV; in stm32_i2s_parse_dt()
1198 i2s->conf = device_get_match_data(&pdev->dev); in stm32_i2s_parse_dt()
1199 if (!i2s->conf) in stm32_i2s_parse_dt()
1200 return -EINVAL; in stm32_i2s_parse_dt()
1202 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_i2s_parse_dt()
1203 if (IS_ERR(i2s->base)) in stm32_i2s_parse_dt()
1204 return PTR_ERR(i2s->base); in stm32_i2s_parse_dt()
1206 i2s->phys_addr = res->start; in stm32_i2s_parse_dt()
1209 i2s->pclk = devm_clk_get(&pdev->dev, "pclk"); in stm32_i2s_parse_dt()
1210 if (IS_ERR(i2s->pclk)) in stm32_i2s_parse_dt()
1211 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk), in stm32_i2s_parse_dt()
1214 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk"); in stm32_i2s_parse_dt()
1215 if (IS_ERR(i2s->i2sclk)) in stm32_i2s_parse_dt()
1216 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk), in stm32_i2s_parse_dt()
1219 if (i2s->conf->get_i2s_clk_parent) { in stm32_i2s_parse_dt()
1220 i2s->set_i2s_clk_rate = stm32_i2s_set_parent_clock; in stm32_i2s_parse_dt()
1222 i2s->set_i2s_clk_rate = stm32_i2s_set_parent_rate; in stm32_i2s_parse_dt()
1223 i2s->put_i2s_clk_rate = stm32_i2s_put_parent_rate; in stm32_i2s_parse_dt()
1226 if (i2s->conf->get_i2s_clk_parent) { in stm32_i2s_parse_dt()
1227 ret = i2s->conf->get_i2s_clk_parent(i2s); in stm32_i2s_parse_dt()
1233 if (of_property_present(np, "#clock-cells")) { in stm32_i2s_parse_dt()
1244 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, 0, in stm32_i2s_parse_dt()
1245 dev_name(&pdev->dev), i2s); in stm32_i2s_parse_dt()
1247 dev_err(&pdev->dev, "irq request returned %d\n", ret); in stm32_i2s_parse_dt()
1252 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in stm32_i2s_parse_dt()
1254 return dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32_i2s_parse_dt()
1266 snd_dmaengine_pcm_unregister(&pdev->dev); in stm32_i2s_remove()
1267 snd_soc_unregister_component(&pdev->dev); in stm32_i2s_remove()
1268 pm_runtime_disable(&pdev->dev); in stm32_i2s_remove()
1277 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); in stm32_i2s_probe()
1279 return -ENOMEM; in stm32_i2s_probe()
1281 i2s->pdev = pdev; in stm32_i2s_probe()
1282 i2s->ms_flg = I2S_MS_NOT_SET; in stm32_i2s_probe()
1283 spin_lock_init(&i2s->lock_fd); in stm32_i2s_probe()
1284 spin_lock_init(&i2s->irq_lock); in stm32_i2s_probe()
1295 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk", in stm32_i2s_probe()
1296 i2s->base, i2s->conf->regmap_conf); in stm32_i2s_probe()
1297 if (IS_ERR(i2s->regmap)) in stm32_i2s_probe()
1298 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap), in stm32_i2s_probe()
1301 ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0); in stm32_i2s_probe()
1303 return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n"); in stm32_i2s_probe()
1305 ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component, in stm32_i2s_probe()
1306 i2s->dai_drv, 1); in stm32_i2s_probe()
1308 snd_dmaengine_pcm_unregister(&pdev->dev); in stm32_i2s_probe()
1312 /* Set SPI/I2S in i2s mode */ in stm32_i2s_probe()
1313 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, in stm32_i2s_probe()
1318 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val); in stm32_i2s_probe()
1323 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val); in stm32_i2s_probe()
1328 dev_err(&pdev->dev, in stm32_i2s_probe()
1330 ret = -EPERM; in stm32_i2s_probe()
1334 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val); in stm32_i2s_probe()
1338 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n", in stm32_i2s_probe()
1343 pm_runtime_enable(&pdev->dev); in stm32_i2s_probe()
1360 regcache_cache_only(i2s->regmap, true); in stm32_i2s_suspend()
1361 regcache_mark_dirty(i2s->regmap); in stm32_i2s_suspend()
1370 regcache_cache_only(i2s->regmap, false); in stm32_i2s_resume()
1371 return regcache_sync(i2s->regmap); in stm32_i2s_resume()
1381 .name = "st,stm32-i2s",
1393 MODULE_ALIAS("platform:stm32-i2s");