1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
62 /* DMA channel select definition */
65 #define MCDT_DMA_CH1_SEL_MASK	GENMASK(7, 4)
66 #define MCDT_DMA_CH1_SEL_SHIFT	4
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
121 	u32 orig = readl_relaxed(mcdt->base + reg);  in sprd_mcdt_update()
125 	writel_relaxed(tmp, mcdt->base + reg);  in sprd_mcdt_update()
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_set_watermark()  argument
131 	u32 reg = MCDT_DAC0_WTMK + channel * 4;  in sprd_mcdt_dac_set_watermark()
140 static void sprd_mcdt_adc_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_set_watermark()  argument
143 	u32 reg = MCDT_ADC0_WTMK + channel * 4;  in sprd_mcdt_adc_set_watermark()
152 static void sprd_mcdt_dac_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_dma_enable()  argument
155 	u32 shift = MCDT_DAC_DMA_SHIFT + channel;  in sprd_mcdt_dac_dma_enable()
163 static void sprd_mcdt_adc_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_dma_enable()  argument
167 		sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(channel), BIT(channel));  in sprd_mcdt_adc_dma_enable()
169 		sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(channel));  in sprd_mcdt_adc_dma_enable()
172 static void sprd_mcdt_ap_int_enable(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_ap_int_enable()  argument
176 		sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, BIT(channel),  in sprd_mcdt_ap_int_enable()
177 				 BIT(channel));  in sprd_mcdt_ap_int_enable()
179 		sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, 0, BIT(channel));  in sprd_mcdt_ap_int_enable()
182 static void sprd_mcdt_dac_write_fifo(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_write_fifo()  argument
185 	u32 reg = MCDT_CH0_TXD + channel * 4;  in sprd_mcdt_dac_write_fifo()
187 	writel_relaxed(val, mcdt->base + reg);  in sprd_mcdt_dac_write_fifo()
190 static void sprd_mcdt_adc_read_fifo(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_read_fifo()  argument
193 	u32 reg = MCDT_CH0_RXD + channel * 4;  in sprd_mcdt_adc_read_fifo()
195 	*val = readl_relaxed(mcdt->base + reg);  in sprd_mcdt_adc_read_fifo()
198 static void sprd_mcdt_dac_dma_chn_select(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_dma_chn_select()  argument
204 				 channel << MCDT_DMA_CH0_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
210 				 channel << MCDT_DMA_CH1_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
216 				 channel << MCDT_DMA_CH2_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
222 				 channel << MCDT_DMA_CH3_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
228 				 channel << MCDT_DMA_CH4_SEL_SHIFT,  in sprd_mcdt_dac_dma_chn_select()
234 static void sprd_mcdt_adc_dma_chn_select(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_dma_chn_select()  argument
240 				 channel << MCDT_DMA_CH0_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
246 				 channel << MCDT_DMA_CH1_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
252 				 channel << MCDT_DMA_CH2_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
258 				 channel << MCDT_DMA_CH3_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
264 				 channel << MCDT_DMA_CH4_SEL_SHIFT,  in sprd_mcdt_adc_dma_chn_select()
270 static u32 sprd_mcdt_dma_ack_shift(u8 channel)  in sprd_mcdt_dma_ack_shift()  argument
272 	switch (channel) {  in sprd_mcdt_dma_ack_shift()
279 		return 4;  in sprd_mcdt_dma_ack_shift()
284 	case 4:  in sprd_mcdt_dma_ack_shift()
295 static void sprd_mcdt_dac_dma_ack_select(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_dac_dma_ack_select()  argument
298 	u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan;  in sprd_mcdt_dac_dma_ack_select()
300 	switch (channel) {  in sprd_mcdt_dac_dma_ack_select()
317 static void sprd_mcdt_adc_dma_ack_select(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_adc_dma_ack_select()  argument
320 	u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan;  in sprd_mcdt_adc_dma_ack_select()
322 	switch (channel) {  in sprd_mcdt_adc_dma_ack_select()
339 static bool sprd_mcdt_chan_fifo_sts(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_chan_fifo_sts()  argument
344 	switch (channel) {  in sprd_mcdt_chan_fifo_sts()
348 	case 4 ... 7:  in sprd_mcdt_chan_fifo_sts()
358 	switch (channel) {  in sprd_mcdt_chan_fifo_sts()
360 	case 4:  in sprd_mcdt_chan_fifo_sts()
385 	return !!(readl_relaxed(mcdt->base + reg) & BIT(shift));  in sprd_mcdt_chan_fifo_sts()
388 static void sprd_mcdt_dac_fifo_clear(struct sprd_mcdt_dev *mcdt, u8 channel)  in sprd_mcdt_dac_fifo_clear()  argument
390 	sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(channel), BIT(channel));  in sprd_mcdt_dac_fifo_clear()
393 static void sprd_mcdt_adc_fifo_clear(struct sprd_mcdt_dev *mcdt, u8 channel)  in sprd_mcdt_adc_fifo_clear()  argument
395 	u32 shift = MCDT_ADC_FIFO_SHIFT + channel;  in sprd_mcdt_adc_fifo_clear()
400 static u32 sprd_mcdt_dac_fifo_avail(struct sprd_mcdt_dev *mcdt, u8 channel)  in sprd_mcdt_dac_fifo_avail()  argument
402 	u32 reg = MCDT_DAC0_FIFO_ADDR_ST + channel * 8;  in sprd_mcdt_dac_fifo_avail()
403 	u32 r_addr = (readl_relaxed(mcdt->base + reg) >>  in sprd_mcdt_dac_fifo_avail()
405 	u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK;  in sprd_mcdt_dac_fifo_avail()
408 		return 4 * (MCDT_FIFO_LENGTH - w_addr + r_addr);  in sprd_mcdt_dac_fifo_avail()
410 		return 4 * (r_addr - w_addr);  in sprd_mcdt_dac_fifo_avail()
413 static u32 sprd_mcdt_adc_fifo_avail(struct sprd_mcdt_dev *mcdt, u8 channel)  in sprd_mcdt_adc_fifo_avail()  argument
415 	u32 reg = MCDT_ADC0_FIFO_ADDR_ST + channel * 8;  in sprd_mcdt_adc_fifo_avail()
416 	u32 r_addr = (readl_relaxed(mcdt->base + reg) >>  in sprd_mcdt_adc_fifo_avail()
418 	u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK;  in sprd_mcdt_adc_fifo_avail()
421 		return 4 * (w_addr - r_addr);  in sprd_mcdt_adc_fifo_avail()
423 		return 4 * (MCDT_FIFO_LENGTH - r_addr + w_addr);  in sprd_mcdt_adc_fifo_avail()
426 static u32 sprd_mcdt_int_type_shift(u8 channel,  in sprd_mcdt_int_type_shift()  argument
429 	switch (channel) {  in sprd_mcdt_int_type_shift()
431 	case 4:  in sprd_mcdt_int_type_shift()
453 static void sprd_mcdt_chan_int_en(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_chan_int_en()  argument
456 	u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);  in sprd_mcdt_chan_int_en()
458 	switch (channel) {  in sprd_mcdt_chan_int_en()
462 	case 4 ... 7:  in sprd_mcdt_chan_int_en()
478 static void sprd_mcdt_chan_int_clear(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_chan_int_clear()  argument
481 	u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);  in sprd_mcdt_chan_int_clear()
483 	switch (channel) {  in sprd_mcdt_chan_int_clear()
487 	case 4 ... 7:  in sprd_mcdt_chan_int_clear()
500 static bool sprd_mcdt_chan_int_sts(struct sprd_mcdt_dev *mcdt, u8 channel,  in sprd_mcdt_chan_int_sts()  argument
503 	u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);  in sprd_mcdt_chan_int_sts()
505 	switch (channel) {  in sprd_mcdt_chan_int_sts()
509 	case 4 ... 7:  in sprd_mcdt_chan_int_sts()
519 	return !!(readl_relaxed(mcdt->base + reg) & BIT(shift));  in sprd_mcdt_chan_int_sts()
527 	spin_lock(&mcdt->lock);  in sprd_mcdt_irq_handler()
531 			struct sprd_mcdt_chan *chan = &mcdt->chan[i];  in sprd_mcdt_irq_handler()
534 			if (chan->cb)  in sprd_mcdt_irq_handler()
535 				chan->cb->notify(chan->cb->data);  in sprd_mcdt_irq_handler()
542 				&mcdt->chan[i + MCDT_ADC_CHANNEL_NUM];  in sprd_mcdt_irq_handler()
545 			if (chan->cb)  in sprd_mcdt_irq_handler()
546 				chan->cb->notify(chan->cb->data);  in sprd_mcdt_irq_handler()
550 	spin_unlock(&mcdt->lock);  in sprd_mcdt_irq_handler()
556  * sprd_mcdt_chan_write - write data to the MCDT channel's fifo
557  * @chan: the MCDT channel
561  * Note: We can not write data to the channel fifo when enabling the DMA mode,
562  * otherwise the channel fifo data will be invalid.
564  * If there are not enough space of the channel fifo, it will return errors
571 	struct sprd_mcdt_dev *mcdt = chan->mcdt;  in sprd_mcdt_chan_write()
573 	int avail, i = 0, words = size / 4;  in sprd_mcdt_chan_write()
576 	spin_lock_irqsave(&mcdt->lock, flags);  in sprd_mcdt_chan_write()
578 	if (chan->dma_enable) {  in sprd_mcdt_chan_write()
579 		dev_err(mcdt->dev,  in sprd_mcdt_chan_write()
581 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_write()
582 		return -EINVAL;  in sprd_mcdt_chan_write()
585 	if (sprd_mcdt_chan_fifo_sts(mcdt, chan->id, MCDT_DAC_FIFO_REAL_FULL)) {  in sprd_mcdt_chan_write()
586 		dev_err(mcdt->dev, "Channel fifo is full now\n");  in sprd_mcdt_chan_write()
587 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_write()
588 		return -EBUSY;  in sprd_mcdt_chan_write()
591 	avail = sprd_mcdt_dac_fifo_avail(mcdt, chan->id);  in sprd_mcdt_chan_write()
593 		dev_err(mcdt->dev,  in sprd_mcdt_chan_write()
595 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_write()
596 		return -EBUSY;  in sprd_mcdt_chan_write()
600 		sprd_mcdt_dac_write_fifo(mcdt, chan->id, *buf++);  in sprd_mcdt_chan_write()
602 	spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_write()
608  * sprd_mcdt_chan_read - read data from the MCDT channel's fifo
609  * @chan: the MCDT channel
613  * Note: We can not read data from the channel fifo when enabling the DMA mode,
622 	struct sprd_mcdt_dev *mcdt = chan->mcdt;  in sprd_mcdt_chan_read()
624 	int i = 0, avail, words = size / 4;  in sprd_mcdt_chan_read()
627 	spin_lock_irqsave(&mcdt->lock, flags);  in sprd_mcdt_chan_read()
629 	if (chan->dma_enable) {  in sprd_mcdt_chan_read()
630 		dev_err(mcdt->dev, "Can not read data when DMA mode enabled\n");  in sprd_mcdt_chan_read()
631 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_read()
632 		return -EINVAL;  in sprd_mcdt_chan_read()
635 	if (sprd_mcdt_chan_fifo_sts(mcdt, chan->id, MCDT_ADC_FIFO_REAL_EMPTY)) {  in sprd_mcdt_chan_read()
636 		dev_err(mcdt->dev, "Channel fifo is empty\n");  in sprd_mcdt_chan_read()
637 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_read()
638 		return -EBUSY;  in sprd_mcdt_chan_read()
641 	avail = sprd_mcdt_adc_fifo_avail(mcdt, chan->id);  in sprd_mcdt_chan_read()
643 		words = avail / 4;  in sprd_mcdt_chan_read()
646 		sprd_mcdt_adc_read_fifo(mcdt, chan->id, buf++);  in sprd_mcdt_chan_read()
648 	spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_read()
649 	return words * 4;  in sprd_mcdt_chan_read()
654  * sprd_mcdt_chan_int_enable - enable the interrupt mode for the MCDT channel
655  * @chan: the MCDT channel
659  * Now it only can enable fifo almost full interrupt for ADC channel and fifo
660  * almost empty interrupt for DAC channel. Morevoer for interrupt mode, user
664  * For ADC channel, user can start to read data once receiving one fifo full
665  * interrupt. For DAC channel, user can start to write data once receiving one
674 	struct sprd_mcdt_dev *mcdt = chan->mcdt;  in sprd_mcdt_chan_int_enable()
678 	spin_lock_irqsave(&mcdt->lock, flags);  in sprd_mcdt_chan_int_enable()
680 	if (chan->dma_enable || chan->int_enable) {  in sprd_mcdt_chan_int_enable()
681 		dev_err(mcdt->dev, "Failed to set interrupt mode.\n");  in sprd_mcdt_chan_int_enable()
682 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_int_enable()
683 		return -EINVAL;  in sprd_mcdt_chan_int_enable()
686 	switch (chan->type) {  in sprd_mcdt_chan_int_enable()
688 		sprd_mcdt_adc_fifo_clear(mcdt, chan->id);  in sprd_mcdt_chan_int_enable()
689 		sprd_mcdt_adc_set_watermark(mcdt, chan->id, water_mark,  in sprd_mcdt_chan_int_enable()
690 					    MCDT_FIFO_LENGTH - 1);  in sprd_mcdt_chan_int_enable()
691 		sprd_mcdt_chan_int_en(mcdt, chan->id,  in sprd_mcdt_chan_int_enable()
693 		sprd_mcdt_ap_int_enable(mcdt, chan->id, true);  in sprd_mcdt_chan_int_enable()
697 		sprd_mcdt_dac_fifo_clear(mcdt, chan->id);  in sprd_mcdt_chan_int_enable()
698 		sprd_mcdt_dac_set_watermark(mcdt, chan->id,  in sprd_mcdt_chan_int_enable()
699 					    MCDT_FIFO_LENGTH - 1, water_mark);  in sprd_mcdt_chan_int_enable()
700 		sprd_mcdt_chan_int_en(mcdt, chan->id,  in sprd_mcdt_chan_int_enable()
702 		sprd_mcdt_ap_int_enable(mcdt, chan->id, true);  in sprd_mcdt_chan_int_enable()
706 		dev_err(mcdt->dev, "Unsupported channel type\n");  in sprd_mcdt_chan_int_enable()
707 		ret = -EINVAL;  in sprd_mcdt_chan_int_enable()
711 		chan->cb = cb;  in sprd_mcdt_chan_int_enable()
712 		chan->int_enable = true;  in sprd_mcdt_chan_int_enable()
715 	spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_int_enable()
722  * sprd_mcdt_chan_int_disable - disable the interrupt mode for the MCDT channel
723  * @chan: the MCDT channel
727 	struct sprd_mcdt_dev *mcdt = chan->mcdt;  in sprd_mcdt_chan_int_disable()
730 	spin_lock_irqsave(&mcdt->lock, flags);  in sprd_mcdt_chan_int_disable()
732 	if (!chan->int_enable) {  in sprd_mcdt_chan_int_disable()
733 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_int_disable()
737 	switch (chan->type) {  in sprd_mcdt_chan_int_disable()
739 		sprd_mcdt_chan_int_en(mcdt, chan->id,  in sprd_mcdt_chan_int_disable()
741 		sprd_mcdt_chan_int_clear(mcdt, chan->id, MCDT_ADC_FIFO_AF_INT);  in sprd_mcdt_chan_int_disable()
742 		sprd_mcdt_ap_int_enable(mcdt, chan->id, false);  in sprd_mcdt_chan_int_disable()
746 		sprd_mcdt_chan_int_en(mcdt, chan->id,  in sprd_mcdt_chan_int_disable()
748 		sprd_mcdt_chan_int_clear(mcdt, chan->id, MCDT_DAC_FIFO_AE_INT);  in sprd_mcdt_chan_int_disable()
749 		sprd_mcdt_ap_int_enable(mcdt, chan->id, false);  in sprd_mcdt_chan_int_disable()
756 	chan->int_enable = false;  in sprd_mcdt_chan_int_disable()
757 	spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_int_disable()
762  * sprd_mcdt_chan_dma_enable - enable the DMA mode for the MCDT channel
763  * @chan: the MCDT channel
764  * @dma_chan: specify which DMA channel will be used for this MCDT channel
767  * Enable the DMA mode for the MCDT channel, that means we can use DMA to
768  * transfer data to the channel fifo and do not need reading/writing data
777 	struct sprd_mcdt_dev *mcdt = chan->mcdt;  in sprd_mcdt_chan_dma_enable()
781 	spin_lock_irqsave(&mcdt->lock, flags);  in sprd_mcdt_chan_dma_enable()
783 	if (chan->dma_enable || chan->int_enable ||  in sprd_mcdt_chan_dma_enable()
785 		dev_err(mcdt->dev, "Failed to set DMA mode\n");  in sprd_mcdt_chan_dma_enable()
786 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_dma_enable()
787 		return -EINVAL;  in sprd_mcdt_chan_dma_enable()
790 	switch (chan->type) {  in sprd_mcdt_chan_dma_enable()
792 		sprd_mcdt_adc_fifo_clear(mcdt, chan->id);  in sprd_mcdt_chan_dma_enable()
793 		sprd_mcdt_adc_set_watermark(mcdt, chan->id,  in sprd_mcdt_chan_dma_enable()
794 					    water_mark, MCDT_FIFO_LENGTH - 1);  in sprd_mcdt_chan_dma_enable()
795 		sprd_mcdt_adc_dma_enable(mcdt, chan->id, true);  in sprd_mcdt_chan_dma_enable()
796 		sprd_mcdt_adc_dma_chn_select(mcdt, chan->id, dma_chan);  in sprd_mcdt_chan_dma_enable()
797 		sprd_mcdt_adc_dma_ack_select(mcdt, chan->id, dma_chan);  in sprd_mcdt_chan_dma_enable()
801 		sprd_mcdt_dac_fifo_clear(mcdt, chan->id);  in sprd_mcdt_chan_dma_enable()
802 		sprd_mcdt_dac_set_watermark(mcdt, chan->id,  in sprd_mcdt_chan_dma_enable()
803 					    MCDT_FIFO_LENGTH - 1, water_mark);  in sprd_mcdt_chan_dma_enable()
804 		sprd_mcdt_dac_dma_enable(mcdt, chan->id, true);  in sprd_mcdt_chan_dma_enable()
805 		sprd_mcdt_dac_dma_chn_select(mcdt, chan->id, dma_chan);  in sprd_mcdt_chan_dma_enable()
806 		sprd_mcdt_dac_dma_ack_select(mcdt, chan->id, dma_chan);  in sprd_mcdt_chan_dma_enable()
810 		dev_err(mcdt->dev, "Unsupported channel type\n");  in sprd_mcdt_chan_dma_enable()
811 		ret = -EINVAL;  in sprd_mcdt_chan_dma_enable()
815 		chan->dma_enable = true;  in sprd_mcdt_chan_dma_enable()
817 	spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_dma_enable()
824  * sprd_mcdt_chan_dma_disable - disable the DMA mode for the MCDT channel
825  * @chan: the MCDT channel
829 	struct sprd_mcdt_dev *mcdt = chan->mcdt;  in sprd_mcdt_chan_dma_disable()
832 	spin_lock_irqsave(&mcdt->lock, flags);  in sprd_mcdt_chan_dma_disable()
834 	if (!chan->dma_enable) {  in sprd_mcdt_chan_dma_disable()
835 		spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_dma_disable()
839 	switch (chan->type) {  in sprd_mcdt_chan_dma_disable()
841 		sprd_mcdt_adc_dma_enable(mcdt, chan->id, false);  in sprd_mcdt_chan_dma_disable()
842 		sprd_mcdt_adc_fifo_clear(mcdt, chan->id);  in sprd_mcdt_chan_dma_disable()
846 		sprd_mcdt_dac_dma_enable(mcdt, chan->id, false);  in sprd_mcdt_chan_dma_disable()
847 		sprd_mcdt_dac_fifo_clear(mcdt, chan->id);  in sprd_mcdt_chan_dma_disable()
854 	chan->dma_enable = false;  in sprd_mcdt_chan_dma_disable()
855 	spin_unlock_irqrestore(&mcdt->lock, flags);  in sprd_mcdt_chan_dma_disable()
860  * sprd_mcdt_request_chan - request one MCDT channel
861  * @channel: channel id
862  * @type: channel type, it can be one ADC channel or DAC channel
864  * Rreturn NULL if no available channel.
866 struct sprd_mcdt_chan *sprd_mcdt_request_chan(u8 channel,  in sprd_mcdt_request_chan()  argument
874 		if (temp->type == type && temp->id == channel) {  in sprd_mcdt_request_chan()
875 			list_del_init(&temp->list);  in sprd_mcdt_request_chan()
890  * sprd_mcdt_free_chan - free one MCDT channel
891  * @chan: the channel to be freed
909 	list_add_tail(&chan->list, &sprd_mcdt_chan_list);  in sprd_mcdt_free_chan()
920 		struct sprd_mcdt_chan *chan = &mcdt->chan[i];  in sprd_mcdt_init_chans()
923 			chan->id = i;  in sprd_mcdt_init_chans()
924 			chan->type = SPRD_MCDT_ADC_CHAN;  in sprd_mcdt_init_chans()
925 			chan->fifo_phys = res->start + MCDT_CH0_RXD + i * 4;  in sprd_mcdt_init_chans()
927 			chan->id = i - MCDT_ADC_CHANNEL_NUM;  in sprd_mcdt_init_chans()
928 			chan->type = SPRD_MCDT_DAC_CHAN;  in sprd_mcdt_init_chans()
929 			chan->fifo_phys = res->start + MCDT_CH0_TXD +  in sprd_mcdt_init_chans()
930 				(i - MCDT_ADC_CHANNEL_NUM) * 4;  in sprd_mcdt_init_chans()
933 		chan->mcdt = mcdt;  in sprd_mcdt_init_chans()
934 		INIT_LIST_HEAD(&chan->list);  in sprd_mcdt_init_chans()
937 		list_add_tail(&chan->list, &sprd_mcdt_chan_list);  in sprd_mcdt_init_chans()
948 	mcdt = devm_kzalloc(&pdev->dev, sizeof(*mcdt), GFP_KERNEL);  in sprd_mcdt_probe()
950 		return -ENOMEM;  in sprd_mcdt_probe()
952 	mcdt->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in sprd_mcdt_probe()
953 	if (IS_ERR(mcdt->base))  in sprd_mcdt_probe()
954 		return PTR_ERR(mcdt->base);  in sprd_mcdt_probe()
956 	mcdt->dev = &pdev->dev;  in sprd_mcdt_probe()
957 	spin_lock_init(&mcdt->lock);  in sprd_mcdt_probe()
964 	ret = devm_request_irq(&pdev->dev, irq, sprd_mcdt_irq_handler,  in sprd_mcdt_probe()
965 			       0, "sprd-mcdt", mcdt);  in sprd_mcdt_probe()
967 		dev_err(&pdev->dev, "Failed to request MCDT IRQ\n");  in sprd_mcdt_probe()
983 		list_del(&chan->list);  in sprd_mcdt_remove()
989 	{ .compatible = "sprd,sc9860-mcdt", },
998 		.name = "sprd-mcdt",
1005 MODULE_DESCRIPTION("Spreadtrum Multi-Channel Data Transfer Driver");