Lines Matching +full:0 +full:x81000
25 #define PCI_TCSEL 0x44
27 #define PCI_CGCTL 0x48
38 #define SOF_HDA_GCAP 0x0
39 #define SOF_HDA_GCTL 0x8
42 #define SOF_HDA_LLCH 0x14
43 #define SOF_HDA_INTCTL 0x20
44 #define SOF_HDA_INTSTS 0x24
45 #define SOF_HDA_WAKESTS 0x0E
47 #define SOF_HDA_RIRBSTS 0x5d
50 #define SOF_HDA_GCTL_RESET BIT(0)
55 #define SOF_HDA_INT_ALL_STREAM 0xff
64 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF
66 #define SOF_HDA_GTS_CAP_ID 0x1
67 #define SOF_HDA_ML_CAP_ID 0x2
69 #define SOF_HDA_PP_CAP_ID 0x3
70 #define SOF_HDA_REG_PP_PPCH 0x10
71 #define SOF_HDA_REG_PP_PPCTL 0x04
72 #define SOF_HDA_REG_PP_PPSTS 0x08
77 #define SOF_HDA_VS_D0I3C 0x104A
80 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
84 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8
86 #define SOF_HDA_SPIB_CAP_ID 0x4
87 #define SOF_HDA_DRSM_CAP_ID 0x5
89 #define SOF_HDA_SPIB_BASE 0x08
90 #define SOF_HDA_SPIB_INTERVAL 0x08
91 #define SOF_HDA_SPIB_SPIB 0x00
92 #define SOF_HDA_SPIB_MAXFIFO 0x04
94 #define SOF_HDA_PPHC_BASE 0x10
95 #define SOF_HDA_PPHC_INTERVAL 0x10
97 #define SOF_HDA_PPLC_BASE 0x10
98 #define SOF_HDA_PPLC_MULTI 0x10
99 #define SOF_HDA_PPLC_INTERVAL 0x10
101 #define SOF_HDA_DRSM_BASE 0x08
102 #define SOF_HDA_DRSM_INTERVAL 0x08
105 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
108 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
111 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
117 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
120 #define SOF_HDA_ADSP_LOADER_BASE 0x80
121 #define SOF_HDA_ADSP_DPLBASE 0x70
122 #define SOF_HDA_ADSP_DPUBASE 0x74
123 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
126 #define SOF_HDA_ADSP_REG_SD_CTL 0x00
127 #define SOF_HDA_ADSP_REG_SD_STS 0x03
128 #define SOF_HDA_ADSP_REG_SD_LPIB 0x04
129 #define SOF_HDA_ADSP_REG_SD_CBL 0x08
130 #define SOF_HDA_ADSP_REG_SD_LVI 0x0C
131 #define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E
132 #define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10
133 #define SOF_HDA_ADSP_REG_SD_FORMAT 0x12
134 #define SOF_HDA_ADSP_REG_SD_FIFOL 0x14
135 #define SOF_HDA_ADSP_REG_SD_BDLPL 0x18
136 #define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C
137 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
140 #define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0)
144 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
145 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
146 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
147 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
148 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
156 #define HDA_DSP_HDA_BAR 0
162 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
164 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
167 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
169 /* SRAM window 0 FW "registers" */
170 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
171 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
173 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
174 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
175 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
177 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
188 #define HDA_DSP_SPIB_DISABLE 0
195 #define FSR_STATE_MASK GENMASK(23, 0)
204 #define FSR_WAIT_FOR_IPC_BUSY 0x1
205 #define FSR_WAIT_FOR_IPC_DONE 0x2
206 #define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3
207 #define FSR_WAIT_FOR_LP_SRAM_OFF 0x4
208 #define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5
209 #define FSR_WAIT_FOR_CSE_CSR 0x6
212 #define FSR_MOD_ROM 0x0
213 #define FSR_MOD_ROM_BYP 0x1
214 #define FSR_MOD_BASE_FW 0x2
215 #define FSR_MOD_LP_BOOT 0x3
216 #define FSR_MOD_BRNGUP 0x4
217 #define FSR_MOD_ROM_EXT 0x5
221 #define FSR_STATE_INIT 0x0
222 #define FSR_STATE_INIT_DONE 0x1
223 #define FSR_STATE_FW_ENTERED 0x5
228 #define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2
229 #define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3
230 #define FSR_STATE_ROM_FW_FW_LOADED 0x4
232 #define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6
233 #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7
234 #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8
235 #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9
236 #define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */
239 #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10
240 #define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11
241 #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12
242 #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13
244 #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20
245 #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21
246 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22
247 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23
248 #define FSR_STATE_ROM_CSE_IPC_DOWN 0x24
253 #define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2
254 #define FSR_STATE_BRINGUP_UNPACK_START 0X3
255 #define FSR_STATE_BRINGUP_IMR_RESTORE 0x4
269 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
270 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
271 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
272 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
273 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
274 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
276 #define HDA_DSP_ROM_IPC_CONTROL 0x01000000
277 #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000
290 #define HDA_DSP_ADSPIC_IPC BIT(0)
291 #define HDA_DSP_ADSPIS_IPC BIT(0)
294 #define HDA_DSP_GEN_BASE 0x0
295 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
296 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
297 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
298 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
299 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
305 #define HDA_DSP_IPC_BASE 0x40
306 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
307 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
308 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
309 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
310 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
313 #define HDA_VS_INTEL_EM2 0x1030
315 #define HDA_VS_INTEL_LTRP 0x1048
316 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
320 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
324 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
328 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
332 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
335 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
343 #define FW_CL_STREAM_NUMBER 0x1
352 #define HDA_DSP_ADSPCS_CRST_SHIFT 0
380 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
383 #define CNL_DSP_IPC_BASE 0xc0
384 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
385 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
386 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
387 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
388 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
389 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
390 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
394 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
398 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
402 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
406 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
410 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
413 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
429 /* Intel HD Audio SRAM Window 0*/
430 #define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000
431 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000
435 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
438 #define APL_SSP_BASE_OFFSET 0x2000
439 #define CNL_SSP_BASE_OFFSET 0x10000
442 #define SSP_DEV_MEM_SIZE 0x1000
452 #define SSP_SSC1_OFFSET 0x4
457 #define HDA_EXT_ADDR 0
471 #define SOF_HDA_PLAYBACK 0
541 /* FW clock config, 0:HPRO, 1:LPRO */
595 #define SOF_STREAM_SD_OFFSET_CRST 0x1
741 #define HDA_CL_STREAM_FORMAT 0x40
813 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } in hda_codec_i915_init()
814 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } in hda_codec_i915_exit()
846 return 0; in hda_sdw_check_lcount_common()
851 return 0; in hda_sdw_check_lcount_ext()
856 return 0; in hda_sdw_check_lcount()
861 return 0; in hda_sdw_startup()
947 return 0; in hda_probes_register()
970 #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */