Lines Matching full:sdev
29 static void hda_dsp_ipc_host_done(struct snd_sof_dev *sdev)
35 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
41 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
47 static void hda_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
53 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
59 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
65 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
68 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
70 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
104 int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
106 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
109 if (hda_ipc4_tx_is_busy(sdev)) {
118 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
121 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE, msg_data->extension);
122 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
131 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
133 struct snd_sof_ipc_msg *msg = sdev->msg;
143 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
162 snd_sof_ipc_get_reply(sdev);
170 struct snd_sof_dev *sdev = context;
175 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
176 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
180 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL,
182 hda_dsp_ipc_dsp_done(sdev);
190 u32 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
196 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL,
201 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
202 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
207 spin_lock_irq(&sdev->ipc_lock);
209 snd_sof_ipc_get_reply(sdev);
210 hda_dsp_ipc_host_done(sdev);
211 snd_sof_ipc_reply(sdev, data->primary);
213 spin_unlock_irq(&sdev->ipc_lock);
215 dev_dbg_ratelimited(sdev->dev,
224 sdev->ipc->msg.rx_data = ¬ification_data;
225 snd_sof_ipc_msgs_rx(sdev);
226 sdev->ipc->msg.rx_data = NULL;
229 hda_dsp_ipc_host_done(sdev);
237 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
240 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
243 hda_dsp_ipc4_send_msg(sdev, hdev->delayed_ipc_tx_msg);
253 struct snd_sof_dev *sdev = context;
263 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
265 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
266 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
267 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
274 trace_sof_intel_ipc_firmware_response(sdev, msg, msg_ext);
277 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
291 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
292 spin_lock_irq(&sdev->ipc_lock);
295 hda_dsp_ipc_get_reply(sdev);
296 snd_sof_ipc_reply(sdev, msg);
299 hda_dsp_ipc_dsp_done(sdev);
301 spin_unlock_irq(&sdev->ipc_lock);
303 dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_READY: %#x\n",
315 trace_sof_intel_ipc_firmware_initiated(sdev, msg, msg_ext);
318 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
324 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
335 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS &&
339 snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext),
343 snd_sof_ipc_msgs_rx(sdev);
346 hda_dsp_ipc_host_done(sdev);
355 dev_dbg_ratelimited(sdev->dev,
364 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
366 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
370 if (sdev->dspless_mode_selected)
374 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
375 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
397 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
403 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
409 int hda_ipc_msg_data(struct snd_sof_dev *sdev,
413 if (!sps || !sdev->stream_box.size) {
414 sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
428 sof_mailbox_read(sdev, hda_stream->sof_intel_stream.posn_offset, p, sz);
435 int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
447 if (posn_offset > sdev->stream_box.size ||
451 hda_stream->sof_intel_stream.posn_offset = sdev->stream_box.offset + posn_offset;
453 dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",
460 void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
465 hda_dsp_get_state(sdev, level);
468 sof_ipc4_intel_dump_telemetry_state(sdev, flags);
470 hda_dsp_dump_ext_rom_status(sdev, level, flags);
474 bool hda_check_ipc_irq(struct snd_sof_dev *sdev)
478 chip = get_chip_info(sdev->pdata);
480 return chip->check_ipc_irq(sdev);
486 void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
495 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
496 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
497 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
498 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
499 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS);
501 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
503 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis);
507 void hda_ipc_dump(struct snd_sof_dev *sdev)
513 hda_ipc_irq_dump(sdev);
516 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
517 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
518 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
522 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
527 void hda_ipc4_dump(struct snd_sof_dev *sdev)
531 hda_ipc_irq_dump(sdev);
533 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
534 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
535 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
536 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
537 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
541 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n",
546 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev)
548 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
552 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req);